IMX93CEC datasheet(58/123 Pages) NXP

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Table 61. ENET2 signal mapping[1]...continued

Pad name

RGMII

Alt mode

RMII

Alt mode

Direction

ENET2_RD1

RGMII_RD1

Alt 0

RMII_RD1

Alt 0

ENET2_RD2

RGMII_RD2

Alt 0

—

Alt 0

ENET2_RD3

RGMII_RD3

Alt 0

—

Alt 0

[1] ENET1 is Ethernet QoS with TSN, while ENET2 is Ethernet MAC.

[2] The signal can be either input or output.

4.12.2.2 RMII mode timing

In RMII mode, enet1.RMII_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock.

Figure 27 shows RMII mode timings. Table 62 describes the timing parameters (M16–M21) shown in the figure.

RMII_REF_CLK

ENET_TX_EN

M16

M17

M18

M19

M20 M21

ENET_RD[1:0]

ENET_TD[1:0]

ENET_RX_ER

ENET_CRS_DV

Figure 27. RMII mode signal timing diagram

Table 62. RMII signal timing[1],[2],[3]

Characteristic

Min.

Max.

Unit

M16

ENET_CLK pulse width high

35%

65%

RMII_REF_CLK

period

M17

RMII_REF_CLK pulse width low

35%

65%

RMII_REF_CLK

period

M18

RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN invalid

—

M19

RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN valid

—

M20

ENET_RX_DATA[1:0], ENET_CRS_DV, ENET_RX_ER to

RMII_REF_CLK setup

—

M21

RMII_REF_CLK to ENET_RX_DATA[1:0], ENET_CRS_DV,

ENET_RX_ER hold

—

[1] The timings assume the following configuration: DSE[5:0] = 001111 and FSEL1[1:0] = 11.

[2] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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