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IMX93CEC Datasheet(PDF) 69 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 69 Page - NXP Semiconductors |
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69 / 123 page  [5] The clock maximum rise/fall time is capped at 60 ns. For lower frequency rise and fall the maximum value is limited at 60 ns, and is not dependent upon the clock frequency. [6] tHD_PP is a Hold time parameter for Push-Pull Mode that has a different value for Master mode vs. Slave mode. In SDR Mode the Hold time parameter is referred to as tHD_SDR. tCF SDA tCR tHD_PP tSU_PP 0.7 x VDD 0.3 x VDD SCL 0.7 x VDD 0.3 x VDD Figure 39. Controller out timing tCF SDA tCR tSCO tSU_PP 0.7 x VDD 0.3 x VDD SCL 0.7 x VDD 0.3 x VDD Figure 40. Target out timing SDA 0.7 x VDD 0.3 x VDD SCL 0.7 x VDD 0.3 x VDD tSU_PP tHD_SDR Figure 41. Controller SDR timing NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 69 / 123 |
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