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Timing diagrams and tolerances required to work with these memories are specified in the respective documents and are not

reprinted here.

Meeting the necessary timing requirements for a DDR memory system is highly dependent on the components chosen and

the design layout of the system as a whole. NXP cannot cover in this document all the requirements needed to achieve a

design that meets full system performance over temperature, voltage, and part variation; PCB trace routing, PCB dielectric

material, number of routing layers used, placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND

and Supply planes layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory

system. Consult the hardware user guide for this device and NXP validated design layouts for information on how to properly

design a PCB for best DDR performance. NXP strongly recommends duplicating an NXP validated design as much as possible

in the design of critical power rails, placement of bulk/decoupling capacitors and DDR trace routing between the processor and

the selected DDR memory. All supporting material is readily available on the device web page on https://www.nxp.com/products/

processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors:IMX9-PROCESSORS.

Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are

not considered marginal parts. A report detailing how the returned part behaved on an NXP validated system will be provided

to the customer as closure to a customer’s reported DDR issue. Customers bear the responsibility of properly designing the

Printed Circuit Board, correctly simulating and modeling the designed DDR system, and validating the system under all expected

operating conditions (temperatures, voltages) prior to releasing their product to market.

Table 34. i.MX 93 DRAM controller supported SDRAM configurations

Parameter

LPDDR4/LPDDR4X

Number of Controllers

Number of Channels

Number of Chip Selects

Bus Width

16-bit

Maximum supported data rate

• Low drive mode

1866 MT/s

• Nominal drive mode

2880 MT/s

• Overdrive mode

3733 MT/s[1]

[1] For 9 x 9 mm package, the maximum date rate of LPDDR4x/LPDDR4 is 3200 MT/s.

4.8.5.1 Clock/data/command/address pin allocations

These processors uses generic names for clock, data, and command address bus; see Table 107 for details about mapping of

clock, data, and command address signals of LPDDR4/LPDDR4X modes.

4.9 Display and graphics

The following sections provide information on display and graphic interfaces.

4.9.1 MIPI D-PHY electrical characteristics

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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