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IMX93CEC Datasheet(PDF) 42 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 42 Page - NXP Semiconductors |
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42 / 123 page  Table 45. Controller mode SAI timing (50 MHz)[1][2][3] Num Characteristic Min Max Unit S1 SAI_MCLK cycle time 20 — ns S2 SAI_MCLK pulse width high/low 40% 60% MCLK period S3 SAI_BCLK cycle time 20 — ns S4 SAI_BCLK pulse width high/low 40% 60% BCLK period S5 SAI_BCLK to SAI_FS output valid — 3 ns S6 SAI_BCLK to SAI_FS output invalid -2 — ns S7 SAI_BCLK to SAI_TXD valid — 3 ns S8 SAI_BCLK to SAI_TXD invalid -2 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 3 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 2 — ns [1] To achieve 50 MHz for BCLK operation, clock must be set in feedback mode. [2] Input timing assumes an input signal slew rate of 3 ns (20%/80%). [3] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm. Unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver. Table 46. Controller mode SAI timing (25 MHz)[1][2] Num Characteristic Min Max Unit S1 SAI_MCLK cycle time 40 — ns S2 SAI_MCLK pulse width high/low 40% 60% MCLK period S3 SAI_BCLK cycle time 40 — ns S4 SAI_BCLK pulse width high/low 40% 60% BCLK period S5 SAI_BCLK to SAI_FS output valid — 3 ns S6 SAI_BCLK to SAI_FS output invalid -2 — ns S7 SAI_BCLK to SAI_TXD valid — 3 ns S8 SAI_BCLK to SAI_TXD invalid -2 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 8 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns [1] Input timing assumes an input signal slew rate of 3 ns (20%/80%). [2] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm. Unterminated, 5-inch microstrip trace on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver. NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 42 / 123 |
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