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MSB IN

BIT 6 . . . 1

Peripheral MSB

Peripheral LSB OUT

SEE

NOTE

see

note

(INPUT)

(CPOL=0)

SCK

(CPOL=1)

PCS

(INPUT)

SOUT

(INPUT)

SIN

(OUTPUT)

LSB IN

BIT 6 . . . 1

NOTE: Not defined

tSCK

tLead

tW SCK

tLag

tSU

tHI

tdis

tHO

tRI/FI

tRO/FO

Figure 37. LPSPI Peripheral mode timing (CPHA = 0)

MSB IN

BIT 6 . . . 1

Peripheral LSB OUT

Peripheral MSB OUT

see

note

(INPUT)

(CPOL=0)

SCK

(CPOL=1)

PCS

(INPUT)

SOUT

(INPUT)

SIN

(OUTPUT)

LSB IN

BIT 6 . . . 1

NOTE: Not defined

tSCK

tLead

tLag

tW SCK

tSU

tHI

tdis

tHO

tRI/FI

tRO/FO

Figure 38. LPSPI Peripheral mode timing (CPHA = 1)

4.12.5 LPI2C timing parameters

LPI2C is a low-power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a controller and/or

as a target.

Table 71. LPI2C module timing parameters[1]

Symbol

Description

Min

Max

Unit

Notes

fSCL

SCL clock frequency

Standard mode (Sm)

100

kHz

[2]

Fast mode (Fm)

400

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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