OR4 datasheet(40/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Special Function Blocks (continued)

Start-Up Logic

The start-up logic block can be conﬁgured to coordi-

nate the relative timing of the release of GSRN, the

activation of all user I/Os, and the assertion of the

DONE signal at the end of conﬁguration. If a start-up

clock is used to time these events, the start-up clock

can come from CCLK, or it can be routed into the start-

up block using upper-left corner routing resources.

Temperature Sensing

The built –in temperature sensing diodes allow junction

temperature to be measured during device operation. A

physical pin (PTEMP) is dedicated for monitoring

device junction temperature. PTEMP works by forcing

a 10 μA current in the forward direction, and then mea-

suring the resulting voltage. A 250 kΩ resistor tied to

3.3 V will approximate the needed 10 μA. The voltage

decreases with increasing temperature at a rate of

approximately –1.44 mV/°C. A typical device with an

85°C device temperature will measure about 640 mV.

Boundary-Scan

The IEEE standards 1149.1 and 1149.2 (IEEE Stan-

dard test access port and boundary-scan architecture)

are implemented in the ORCA series of FPGAs. It

allows users to efﬁciently test the interconnection

between integrated circuits on a PCB as well as test

the integrated circuit itself. The IEEE 1149 standard is

a well-deﬁned protocol that ensures interoperability

among boundary-scan (BSCAN) equipped devices

from different vendors.

Series 4 FPGAs are also compliant to IEEE standard

1532/D1. This standard for boundary-scan based in-

system conﬁguration of programmable devices pro-

vides a standardized programming access and meth-

odology for FPGAs. A device, or set of devices,

implementing this standard may be programmed, read

back, erased veriﬁed, singly or concurrently, with a

standard set of resources.

The IEEE 1149 standards deﬁne a test access port

(TAP) that consists of a four-pin interface with an

optional reset pin for boundary-scan testing of inte-

grated circuits in a system. The ORCA Series FPGA

provides four interface pins: test data in (TDI), test

mode select (TMS), test clock (TCK), and test data out

(TDO). The PRGM pin used to reconﬁgure the device

also resets the boundary-scan logic.

The user test host serially loads test commands and

test data into the FPGA through these pins to drive out-

puts and examine inputs. In the conﬁguration shown in

Figure 26, where boundary-scan is used to test ICs,

test data is transmitted serially into TDI of the ﬁrst

BSCAN device (U1), through TDO/TDI connections

between BSCAN devices (U2 and U3), and out TDO of

the last BSCAN device (U4). In this conﬁguration, the

TMS and TCK signals are routed to all boundary-scan

ICs in parallel so that all boundary-scan components

operate in the same state. In other conﬁgurations, mul-

tiple scan paths are used instead of a single ring. When

multiple scan paths are used, each ring is indepen-

dently controlled by its own TMS and TCK signals.

Figure 26 provides a system interface for components

used in the boundary-scan testing of PCBs. The three

major components shown are the test host, boundary-

scan support circuit, and the devices under test

(DUTs). The DUTs shown here are ORCA Series

FPGAs with dedicated boundary-scan circuitry. The

test host is normally one of the following: automatic test

equipment (ATE), a workstation, a PC, or a micropro-

cessor.

5-5972(F)

Key:BSC = boundary-scan cell, BDC = bidirectional data cell, and

DCC = data control cell.

Figure 25. Printed-Circuit Board with

Boundary-Scan Circuitry

INSTRUCTION

TDO

BYPASS

TCK TMS TDI

SCAN

OUT

SCAN

OUT

SCAN

OUT

BSC

BDC

DCC

SCAN

OUT

SCAN

TAPC

p_in

p_out

p_in

p_ts

p_out

p_ts

p_in

p_out

p_ts

p_out

p_ts

PL[ij]

PT[ij]

PR[ij]

PB[ij]

BDC

DCC

PLC

ARRAY

BDC

DCC

BDC

DCC

BSC

SEE ENLARGED VEIW BELOW

TMS TDI

TCK

TDO

TMS TDI

TCK

TDO

TMS TDI

TCK

TDO

TMS TDI

TCK

TDO

TDI

TCK

TDO

TMS

net a

net b

net c

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