OR4 datasheet(82/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Table 41. Embedded Block RAM (EBR) Timing Characteristics (512 x 18) Quad-Port RAM Mode

OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 ˚C

OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 ˚C

Note: A complete listing of EBR Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.

Table 42. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics

OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 ˚C

OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 ˚C

Note: A complete listing of SLIC Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.

Parameter

Symbol

Speed

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

Write Operation for RAM Mode:

Maximum Write Clock Frequency

Write Data to Write Clock Setup Time

Write Address to Write Clock Setup Time

EBRWCLK_FRQ

D*_CKW*_SET

A*_CKW*_SET

—

0.39

0.60

200.0

—

0.37

0.58

217.0

—

0.34

0.52

225.0

—

MHz

Async Read Operation for RAM Mode:

Data Out Valid After Read Address

EBR_RA_DEL

—

4.72

—

4.48

—

4.06

Sync Read Operation for RAM Mode:

Maximum Read Clock Frequency

Read Address to Read Clock Setup Time

(OUTREG Mode)

Read Clock to Data Out (IOREG or OUT-

REG modes)

EBRRCLK_FRQ

AR*_CKR*_SET

CKR*_Q*_DEL

—

0.59

—

200.0

—

2.39

—

0.56

—

217.0

—

2.27

—

0.51

—

225.0

—

2.06

MHz

Parameter

Symbol

Speed

Unit

-1

-2

-3

Min

Max

Min Max Min Max

3-Statable BIDIs

BIDI Buffer Delay

BIDI 3-state Enable/Disable Delay

BUF_DEL

TRI_DEL

—

0.35

0.39

—

0.35

—

0.32

Decoder

Decoder Delay (BR[9:8], BL[9:8] to DEC)

DEC_DEL

—

0.89

—

0.81

—

0.73

—

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