OR4 datasheet(53/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Phase-Locked Loops (PLLs)

There are eight PLLs available to perform many clock modiﬁcation and clock conditioning functions on the Series 4

FPGAs. Six of the PLLs are programmable allowing the user the ﬂexibility to conﬁgure the PLL to manipulate the

frequency, phase, and duty cycle of a clock signal. Four of the programmable PLLs (PPLLs) are capable of manipu-

lating and conditioning clocks from 15 MHz to 200 MHz and two others (HPPLLs) are capable of manipulating and

conditioning clocks from 60 MHz to 420 MHz. Frequencies can be adjusted from 1/64x to 64x the input clock fre-

quency. Each programmable PLL provides two outputs that have different multiplication factors with the same

phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An

automatic delay compensation mode is available for phase delay. Each PPLL and HPPLL provides two outputs that

can have programmable (45 degree increments) phase differences.

The PPLLs and HPPLLs can be utilized to eliminate skew between the clock input pad and the internal clock inputs

across the entire device. Both the PPLLS or the HPPLLs can drive onto the primary and secondary clock networks

inside the FPGA. Each can take a clock input from the dedicated pad or differential pair of pads in its corner or from

general routing resources.

Functionality of the PPLLs and HPPLLs is programmed during operation through a control register internal to the

FPGA array or via the conﬁguration bit stream. The embedded system bus enables access to these registers (see

Table 23). There is also a PLL output signal, LOCK, that indicates a stable output clock state.

Table 27. PPLL Speciﬁcations

Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system

designs. These DPLLs meet ITU-T G.811 primary clocking speciﬁcations and enable system designers to target

very tightly speciﬁed clock conditioning not available in the programmable PPLLs. They also provide enhanced jitter

ﬁltering to reduce the amount of input jitter that is transferred to the PLL output when used in any application.

DPLLs are targeted to low-speed DS1 and E1 networking systems (PLL1) and high-speed SONET/SDH network-

ing STS-3 and STM-1 networking systems (PLL2).

Parameter

Min

Nom

Max

Unit

VDD15

1.425

1.5

1.575

VDD33

3.0

3.3

3.6

Operating Temp

–40

—

125

Input Clock Frequency

(No division)

PPLL

2.0

—

200

MHz

HPPLL

7.5

—

420

Output Clock Frequency

PPLL

—

200

MHz

HPPLL

—

420

Input Duty Cycle

—

Output Duty Cycle

Lock Time

—

<50

—

μs

Frequency Multiplication

Up to 64x

—

Frequency Division

Down to 1/64x

—

Duty Cycle Adjust of Output Clock

12.5, 25, 37.5, 50, 62.5, 75, 87.5

Delay Adjust of Output Clock

0, 45, 90, 135, 180, 225, 270, 315

degrees

Phase Shift Between MCLK and NCLK

0, 45, 90, 135, 180, 225, 270, 315

degrees

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