OR4 datasheet(77/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Power Estimation

A spreadsheet is available in ispLEVER for detailed

power estimates based on circuit implementation

details from ispLEVER and user inputs. A quick esti-

mate of power dissipation for a Series 4 device is now

presented.

Estimating Power Dissipation

The total operating power dissipated is estimated by

adding the standby (IDDSB), internal, and external

power dissipated. The internal and external power is

the power consumed in the PLCs and PICs, respec-

tively. In general, the standby power is small and may

be neglected. The total operating power is as follows:

PT = Σ PINT + Σ PIO + PCLK

The internal operating power is made up of two parts:

clock generation and PFU/EBR/PIO power. The PFU/

EBR/PIO power can be estimated per output based

upon the number of PFU/EBR/PIO outputs switching

when driving a typical fanout (three X6 lines and nine

X1 lines).

PINT = 0.015 mW/MHz

For each PFU/EBR/PIO output that switches, 0.015

mW/MHz needs to be multiplied times the frequency (in

MHz) that the output switches. Generally, this can be

estimated by using the clock rate multiplied by some

activity factor; for example, 20%.

The power dissipated by clocks is due to either global

primary clock networks or secondary/edge clock net-

works. Their power has a ﬁxed component and a vari-

able component based on the number of PFUs, PIOs,

or EBRs that use that clock as follows:

■

Primary: 0.143 mW/MHz + (0.0033mW/MHz x num-

ber of blocks driven)

■

Secondary: 0.06 mW/MHz + (0.0029mW/MHz x

number of blocks driven)

Clock power is calculated from these equations by mul-

tiplying times the clock frequency in MHz. Note that an

activity factor (i.e., 100% activity) is not used to calcu-

late clock power.

The device I/O power dissipated is the sum of the

power dissipated in the four PIOs in the PIC. This con-

sists of power dissipated by inputs and ac power dissi-

pated by outputs. The power dissipated in each PIO

depends on whether it is conﬁgured as an input, out-

put, or input/output. If a PIO is operating as an output,

then there is a power dissipation component for PIN, as

well as POUT. This is because the output feeds back to

the input.

The power dissipated by a LVCMOS2 input buffer is

(VIH = VDD – 0.3 V or higher) estimated as:

PIN = 0.09 mW/MHz

The ac power dissipation from a LVCMOS2 output or

bidirectional is estimated by the following:

POUT = (CL + 5.0 pF) x VDD2 x F Watts

where the unit for CL (the output capacitive load) is Far-

ads, and the unit for F is Hz.

For all other I/O buffer types other than LVCMOS2, see

the detailed power estimation spreadsheet available in

ispLEVER.

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