OR4 datasheet(13/152 Pages) LATTICE

13 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Programmable Logic Cells (continued)

5-9736(F)a

Figure 7. MUX 8x1

Softwired LUT submode uses F4, F5 and F6 LUTs and internal PFU feedback routing to generate complex logic

functions up to three LUT-levels deep. Multiplexers can be independently conﬁgured to route certain LUT outputs to

the input of other LUTs. In this manner, very complex logic functions, some of up to 22 inputs, can be implemented

in a single PFU at greatly enhanced speeds.

It is important to note that an LUT output that is fed back for softwired use is still available to be registered or output

from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equa-

tion need only be generated once, and PLC routing resources will not be required to use it in the larger equation.

K7_0

K7_1

K7_2

F5D

LUT4

K6_0

K6_1

K6_2

LUT4

K5_0

K5_1

K5_2

K4_0

K4_1

K4_2

F5C

LUT4

K3_0

K3_1

K3_2

F5B

LUT4

K2_0

K2_1

K2_2

LUT4

K1_0

K1_1

K1_2

K0_0

K0_1

K0_2

F5A

LUT4

MUX8x1

4x1

MUX

4x1

MUX

[LUT647]

MUX8x1

[LUT603]

OR4 Datasheet(PDF) 13 Page - Lattice Semiconductor

OR4 Datasheet(HTML) 13 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL