OR4 datasheet(6/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Product Description (continued)

Note: For FPSCs, all I/Os and the four PLLs on the right side of the device are replaced with the embedded core.

5-7536(F)a

Figure 1. Series 4 Top Level Diagram

Programmable Logic Cells

The PLCs are arranged in an array of rows and columns. The location of a PLC is indicated by its row and column

so that a PLC in the second row and the third column is R2C3. The array of actual PLCs for every device begins

with R3C2 in all Series 4 generic FPGAs. PIOs are located on all four sides of the FPGA. Every group of four PIOs

on the device edge have an associated PIC.

The PLC consists of a PFU, SLIC, and routing resources. Each PFU within a PLC contains eight

4-input (16-bit) LUTs, eight latches/FFs, and one additional FF that may be used independently or with arithmetic

functions. The PFU is the main logic element of the PLC, containing elements for both combinatorial and sequential

logic. Combinatorial logic is done in LUTs located in the PFU. The PFU can be used in different modes to meet dif-

ferent logic requirements. The LUTs twin-quad architecture provides a conﬁgurable medium-/large-grain architec-

ture that can be used to implement from one to eight independent combinatorial logic functions or a large number

of complex logic functions using multiple LUTs. The ﬂexibility of the LUT to handle wide input functions, as well as

multiple smaller input functions, maximizes the gate count per PFU while increasing system speed.

The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently.

Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.

LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit

modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be con-

ﬁgured as a synchronous 32x4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT

outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable

clock polarity, clock enables, and local set/reset.

EMBEDDED

SYSTEM BUS

PLC

MICROPROCESSOR

INTERFACE (MPI)

PFU

SLIC

FPGA/SYSTEM

BUS INTERFACE

PLLs

EMBEDDED

BLOCK RAM

HIGH-SPEED I/Os

CLOCK PINS

PIO

REPLACED BY

EMBEDDED IP

CORE FOR FPSCs

(ALL 4 SIDES)

(ALL 4

CORNERS)

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