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OR4 Datasheet(PDF) 89 Page - Lattice Semiconductor |
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OR4 Datasheet(HTML) 89 Page - Lattice Semiconductor |
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89 / 152 page  Lattice Semiconductor 89 Data Sheet May, 2006 ORCA Series 4 FPGAs Timing Characteristics (continued) Table 51. Primary CLK (PCLK) Setup/Hold Time without on-chip PLLs (Pin-to-Pin) OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C Notes: 1. The pin-to-pin timing parameters in this table will match ispLEVER if the clock delay multiplier in the setup preference is set to 0.95 for setup time and 1.05 for hold time. 2. Timing is without the use of the phase-locked loops (PLLs) or PIO input FF cycle stealing delays (which can provide reductions in setup time at the expense of hold time). 3. This setup/hold time is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer delay, the clock routing to the PIO CLK input, the setup/hold time of the PIO FF (with the data input delay disabled) and the LVTTL (3.3 V) input data buffer to PIO FF delay. The PCLK input clock is connected at the semi-dedicated primary clock input pins. 4. For timing improvements using other I/O buffer types for the input clock buffer or input data buffer, see Table 53. 5-4847(F).a Figure 51. Input to Primary Clock Setup/Hold Time Description Device Speed Unit -1 -2 -3 Min Max Min Max Min Max Input to PCLK Setup Time, Input Data Delay Enabled OR4E02 OR4E04 OR4E06 4.42 4.24 4.11 — — — 4.41 4.26 4.14 — — — 4.04 3.90 3.80 — — — ns ns ns Input to PCLK Setup Time, No Input Data Delay OR4E02 OR4E04 OR4E06 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — ns ns ns Input to PCLK Hold Time, Input Data Delay Enabled OR4E02 OR4E04 OR4E06 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — ns ns ns Input to PCLK Hold Time, No Input Data Delay OR4E02 OR4E04 OR4E06 4.98 5.22 5.43 — — — 4.50 4.71 4.89 — — — 4.07 4.26 4.42 — — — ns ns ns Input Delay Adjustments from PIO Cycle Stealing (used to reduce setup time by the min value shown): One Delay Cell Two Delay Cells Three Delay Cells All All All — — — 0.89 1.64 2.43 — — — 0.70 1.29 1.98 — — — 0.64 1.18 1.80 ns ns ns Q D PCLK INPUT PIO FF |
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