OR4 datasheet(49/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Microprocessor Interface (MPI)

The Series 4 FPGAs have a dedicated synchronous

MPI function block. The MPI is programmable to oper-

ate with PowerPC/PowerQUICC MPC860/MPC8260

series microprocessors. The MPI implements an 8-,

16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to

the host processor (PowerPC) that can be used for

conﬁguration and readback of the FPGA as well as for

user-deﬁned data processing and general monitoring

of FPGA functions. In addition to dedicated-function

registers, the MPI bridges to the AMBA embedded sys-

tem bus through which the PowerPC bus master can

access the FPGA conﬁguration logic, EBR and other

user logic. There is also capability to interrupt the host

processor either by a hard interrupt or by having the

host processor poll the MPI and the embedded system

bus.

The control portion of the MPI is available following

powerup of the FPGA if the mode pins specify MPI

mode, even if the FPGA is not yet conﬁgured. The

width of the data port is selectable among 8-, 16-, or

32-bit and the parity bus can be 1-, 2-, or 4-bit. In con-

ﬁguration mode the data and parity bus width are

related to the state of the M[0:3] mode pins. For post-

conﬁguration use, the MPI must be included in the con-

ﬁguration bit stream by using an MPI library element in

your design from the ORCA macro library, or by setting

the bit of the MPI conﬁguration control register prior to

the start of conﬁguration. The user can also enable and

disable the parity bus through the conﬁguration bit

stream. These pads can be used as general I/O when

they are not needed for MPI use.

Table 22 shows the interface signals that are used to

interface Series 4 devices to a PowerPC MPC860/

MPC8260 device. More information is available in the

Series 4 MPI and System Bus application note.

The ORCA FPGA is a memory-mapped peripheral to

the PowerPC processor. The MPI interfaces to the

user-programmable FPGA logic using the AMBA

embedded system bus.The MPI has access to a series

of addressable registers made accessible by the AMBA

system bus that provide MPI control and status, conﬁg-

uration and readback data transfer, FPGA device iden-

tiﬁcation, and a dedicated user scratchpad register. All

registers are 8 bits wide. The address map for these

registers and the user-logic address space utilize the

same registers as the AMBA embedded system bus.

Embedded System Bus (ESB)

Implemented using the open standard, on-chip AMBA-

AHB 2.0 speciﬁcation bus, the Series 4 devices con-

nects all the FPGA elements together with a standard-

ized bus framework. The ESB facilitates

communication among MPI, conﬁguration, EBRs, and

user logic in all the generic FPGA devices. AHB serves

the need for high-performance system-on-chip

(SoC) as well as aligning with current synthesis design

ﬂows. Multiple bus masters optimizes system perfor-

mance by sharing resources between different bus

masters such as the MPI and conﬁguration logic. The

wide data bus conﬁguration of 32-bits with 4-bit parity

supports the high-bandwidth of data-intensive applica-

tions of using the wide on-chip memory. AMBA

enhances a reusable design methodology by deﬁning a

common backbone for IP modules.

The ESB is a synchronous bus that is driven by either

the MPI clock, internal oscillator, CCLK (slave conﬁgu-

ration modes), TCK (JTAG conﬁguration modes), or by

a user clock from routing. In FPSCs, a clock from the

embedded block can also drive the MPI clock. During

initial conﬁguration and reconﬁguration the bus clock is

defaulted to the conﬁguration clock. The post conﬁgu-

ration clock source is set during conﬁguration. The user

has the ability to program several slaves through the

user logic interface. Embedded block RAM also inter-

faces seamlessly to the system bus.

A single bus arbiter controls the trafﬁc on the bus by

ensuring only one master has access to the bus at any

time. The arbiter monitors a number of different

requests to use the bus and decides which request is

currently the highest priority. The conﬁguration modes

have the highest priority and overrides all normal user

modes. Priority can be programmed between MPI and

user logic at conﬁguration in generic FPGAs. If no pri-

ority is set a round-robin approach is used by granting

the next requesting master in a rotating ﬁxed order.

Several interfaces exist between the ESB and other

FPGA elements. The MPI interface acts as a bridge

between the external microprocessor bus and ESB.

The MPI may work in an independent clock domain

from the ESB if the ESB clock is not sourced from the

external microprocessor clock. Pipelined operation

allows high-speed memory interface to the EBR and

peripheral access without the requirement for addi-

tional cycles on the bus. Burst transfers allow optimal

use of the memory interface by giving advance infor-

mation of the nature of the transfers.

Table 23 is a listing of the ESB register ﬁle and brief

descriptions. Table 24 shows the system interrupt reg-

isters and Table 25 and Table 26 show the FPGA status

and command registers, all with brief descriptions.

More information is available in the Series 4 MPI and

System Bus application note.

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