OR4 datasheet(85/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Table 45. Primary Clock Skew to any PFU or PIO Register

OR4Exx commercial/industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, –40 °C < TJ < +125 °C

Table 46. Secondary Clock to Output Delay without on-chip PLLs (Pin-to-Pin)

OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C.;

CL = 30 pF

OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C.;

CL = 30 pF.

Notes:

1. Timing is without the use of the phase-locked loops (PLLs).

2. This clock delay is for a fully routed clock tree that uses the secondary clock network. It includes the LVTTL (3.3 V) input clock buffer, the clock

routing to the PIO CLK input, the clock→Q of the FF, and the delay through the LVTTL (3.3 V) data output buffer. An SCLK input clock can be

at any input pin.

3. For timing improvements using other I/O buffer types for the input clock buffer or output data buffer, see Table 53 and Table 55.

5-4846(F).a

Figure 47. Secondary CLK to Output Delay

Description

Device

Speed

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

Primary Clock Skew Information (pos edge to

pos edge or neg edge to neg edge)

OR4E02

OR4E04

OR4E06

—

110

120

—

105

—

100

Primary Clock Skew Information (pos edge to

pos edge, neg edge to neg edge, pos edge to

neg edge or neg edge to pos edge)

OR4E02

OR4E04

OR4E06

—

265

285

300

—

190

210

220

—

180

200

210

Description

Device

Speed

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

SCLK → OUTPUT Pin (LVTTL-12 mA Fast,

Output within 6 PICs of SCLK input)

All

—

7.22

—

6.70

—

6.06

Additional Delay per each extra 6 PICs per

clock route direction.

All

—

0.36

—

0.38

—

0.34

OUTPUT (30 pF LOAD)

SCLK

PIO FF

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