OR4 datasheet(97/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Table 61. Asynchronous Peripheral Configuration Mode Timing Characteristics

OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ <

+125 °C; CL = 30 pF.

* The smaller delay is for fast asynchronous peripheral mode (mode pins M[3:0]=”0101”) and the larger delay is for slow asynchronous periph-

eral mode (mode pins M[3:0]=”1101”).

† This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin.

Note: Serial data is transmitted out on DOUT on the rising edge of CCLK after the byte is input on D[7:0].

D[2:0] timing is the same as the write data portion of the D[7:3] waveform because D[2:0] are not enabled by RD.

5-4533(F).b

Figure 56. Asynchronous Peripheral Configuration Mode Timing Diagram

Parameter

Symbol

Min

Max

Unit

WR, CS0, and CS1 Pulse Width

TWR

10.00

60.00 / 500.00*

D[7:0] Setup Time:

0.00

—

RDY Delay

TRDY

—

10.00

RDY Low

1.00

8.00

CCLK Periods

Earliest WR After RDY Goes High†

TWR2

0.00

—

RD to D[7:0] Enable/Disable

TDEN

—

10.00

CCLK to DOUT

—

5.00

CS1

D[7:3]

CCLK

DOUT

CS0

RDY

TWR

TRDY

PREVIOUS BYTE

TWR2

WRITE DATA

TDEN

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