OR4 datasheet(48/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Special Function Blocks (continued)

Readback can be initiated at an address other than

frame 0 via the new MPI control registers (see the MPI

section for more information). In all cases, readback is

performed at sequential addresses from the start

address.

It should be noted that the RD_DATA output pin is also

used as the dedicated boundary-scan output pin, TDO.

If this pin is being used as TDO, the RD_DATA output

from readback can be routed internally to any other pin

desired. The RD_CFG input pin is also used to control

the global 3-state (TS_ALL) function. Before and during

conﬁguration, the TS_ALL signal is always driven by

the RD_CFG input and readback is disabled. After con-

ﬁguration, the selection as to whether this input drives

the readback or global 3-state function is determined

by a set of bit stream options. If used as the RD_CFG

input for readback, the internal TS_ALL input can be

routed internally to be driven by any input pin.

The readback frame contains the conﬁguration data

and the state of the internal logic. During readback, the

value of all registered PFU and PIO outputs can be

captured. The following options are allowed when

doing a capture of the PFU outputs.

■

Do not capture data (the data written to the RAMs,

usually 0, will be read back).

■

Capture data upon entering readback.

■

Capture data based upon a conﬁgurable signal inter-

nal to the FPGA. If this signal is tied to logic 0, cap-

ture RAMs are written continuously.

■

Capture data on either options two or three above.

The readback frame has an identical format to that of

the conﬁguration data frame, which is discussed later

in the Conﬁguration Data Format section. If LUT mem-

ory is not used as RAM and there is no data capture,

the readback data (not just the format) will be identical

to the conﬁguration data for the same frame. This

eases a bitwise comparison between the conﬁguration

and readback data. The conﬁguration header, including

the length count ﬁeld, is not part of the readback frame.

The readback frame contains bits in locations not used

in the conﬁguration. These locations need to be

masked out when comparing the conﬁguration and

readback frames. The development system optionally

provides a readback bit stream to compare to readback

data from the FPGA. Also note that if any of the LUTs

are used as RAM and new data is written to them,

these bits will not have the same values as the original

conﬁguration data frame either.

Global 3-State Control (TS_ALL)

To increase the testability of the ORCA Series FPGAs,

the global 3-state function (TS_ALL) disables the

device. The TS_ALL signal is driven from either an

external pin or an internal signal. Before and during

conﬁguration, the TS_ALL signal is driven by the input

pad RD_CFG. After conﬁguration, the TS_ALL signal

can be disabled, driven from the RD_CFG input pad, or

driven by a general routing signal in the upper right cor-

ner. Before conﬁguration, TS_ALL is active-low; after

conﬁguration, the sense of TS_ALL can be inverted.

The following occur when TS_ALL is activated:

■

All of the user I/O output buffers are 3-stated, the

user I/O input buffers are pulled up (with the pull-

down disabled), and the input buffers are conﬁgured

with TTL input thresholds.

■

The TDO/RD_DATA output buffer is 3-stated.

■

The RD_CFG, RESET, and PRGM input buffers

remain active with a pull-up.

■

The DONE output buffer is 3-stated, and the input

buffer is pulled up.

OR4 Datasheet(PDF) 48 Page - Lattice Semiconductor

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