OR4 datasheet(96/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Table 60. Master Parallel Configuration Mode Timing Characteristics

OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ <

+125 °C; CL = 30 pF.

Note:

The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.

Serial data is transmitted out on DOUT two CCLK cycles after the byte is input on D[7:0].

2706(F)

Figure 55. Master Parallel Configuration Mode Timing Diagram

Parameter

Symbol

Min

Max

Unit

RCLK to Address Valid

TAV

—

10.00

D[7:0] Setup Time to RCLK High

10.00

—

D[7:0] Hold Time to RCLK High

0.00

—

RCLK Low Time

TCL

7.00

CCLK cycles

RCLK High Time

TCH

1.00

CCLK cycles

CCLK to DOUT

—

5.00

A[21:0]

RCLK

D[7:0]

TCL

TCH

TAV

CCLK

DOUT

BYTE N

BYTE N + 1

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