OR4 datasheet(18/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Programmable Logic Cells (continued)

Memory Mode

The Series 4 PFU can be used to implement a 32x4 (128-bit) synchronous, dual-port RAM). A block diagram of a

PFU in memory mode is shown in Figure 12. This RAM can also be conﬁgured to work as a single-port memory

and because initial values can be loaded into the RAM during conﬁguration, it can also be used as a ROM.

5-5969(F)a

1. CLK[0:1] are commonly connected in memory mode.

2. CE1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled).

CE0 = write port enable 0; CE0 = 0, wren = 0; CE0 = 1, wren = CE1.

LSR0 = write port enable 1; LSR0 = 0, wren = CE0; LSR0 = 1, wren = CE1.

Figure 12. Memory Mode

CIN(WA1)

KZ[3:0]

F5[A:D]

D Q

DIN7(WA3)

D Q

DIN5(WA2)

D Q

DIN3(WA1)

D Q

DIN1(WA0)

D Q

DIN6(WD3)

D Q

DIN4(WD2)

D Q

DIN2(WD1)

D Q

DIN0(WD0)

D Q

CE0, LSR0

S/E

CLK[0:1]

WRITE

READ

D Q

WRITE

RAM CLOCK

ADDRESS[4:0]

DATA[3:0]

ENABLE

(SEE NOTE 2.)

CE1

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