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OR4 Datasheet(PDF) 98 Page - Lattice Semiconductor |
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OR4 Datasheet(HTML) 98 Page - Lattice Semiconductor |
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98 / 152 page ![]() 98 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Timing Characteristics (continued) Table 62. Slave Serial Configuration Mode Timing Characteristics OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +125 °C; CL = 30 pF. Note: Serial configuration data is transmitted out on DOUT on the rising edge of CCLK after it is input on DIN. 5-4535(F).b Figure 57. Slave Serial Configuration Mode Timing Diagram Parameter Symbol Min Max Unit DIN Setup Time TS 5.00 — ns DIN Hold Time TH 0.00 — ns CCLK High Time TCH 5.00 — ns CCLK Low Time TCL 5.00 — ns CCLK Frequency FC — 100.00 MHz CCLK to DOUT TD — 5.00 ns DIN CCLK DOUT TD TS TH TCL TCH BIT N BIT N |
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