OR4 datasheet(91/152 Pages) LATTICE

91 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Table 53. Microprocessor Interface (MPI) Timing Characteristics

OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, –40 °C < TJ < + 125 °C

Table 54. Embedded System Bus (ESB) Timing Characteristics

OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, –40 °C < TJ < + 125 °C

Table 55. Phase-Locked Loop (PLL) Timing Characteristics

See the section on PLLs in this data sheet and in the PLL application note for timing information.

Table 56. Boundary-Scan Timing Characteristics

OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, –40 °C < TJ < +125 °C;

CL = 30 p

5-6764(F)

Figure 52. Boundary-Scan Timing Diagram

Parameter

Symbol

Min

Max

Unit

MPI Control (STRB, WR, etc.) to MPI_CLK Setup Time

MPICTRL_SET

7.7

—

MPI Address to MPI_CLK Setup Time

MPIADR_SET

3.5

—

MPI Write Data to MPI_CLK Setup Time

MPIDAT_SET

3.4

—

All Hold Times

MPI_HLD

0.0

—

MPI_CLK to MPI Control (TA, TEA, RETRY)

MPICTRL_DEL

—

8.3

MPI_CLK to MPI Data (8-bit)

MPIDAT8_DEL

—

9.2

MPI_CLK to MPI Data (16-bit)

MPIDAT16_DEL

—

10.0

MPI_CLK to MPI Data (32-bit)

MPIDAT32_DEL

—

10.6

MPI_CLK Frequency

MPI_CLK_FRQ

—

MHz

Parameter

Symbol

Min

Max

Unit

ESB_CLK Frequency (no wait states)

ESB_CLK Frequency (with wait states)

ESB_CLK_FRQ

—

100

MHz

Parameter

Symbol

Min

Max

Unit

TDI/TMS to TCK Setup Time

10.0

—

TDI/TMS Hold Time from TCK

0.0

—

TCK Low Time

TCL

25.0

—

TCK High Time

TCH

25.0

—

TCK to TDO Delay

—

10.0

TCK Frequency

TTCK

—

20.0

MHz

TCK

TMS

TDI

TDO

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