OR4 datasheet(51/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Microprocessor Interface (continued)

Table 23. Embedded System Bus/MPI Registers

Note: RO = Read Only, R/W = Read/Write

Table 24. Interrupt Register Space Assignments

Note: RO = Read Only, R/W = Read/Write.

For internal system bus, bit 7 is most signiﬁcant bit, for MPI bit 0 is most signiﬁcant bit.

Byte

Read/Write Initial Value

Description

03-00

—

32-bit device ID

07-04

R/W

—

Scratchpad register

0B-08

R/W

—

Command register

0F-0C

—

Status register

R/W

—

Interrupt enable register – MPI

R/W

—

Interrupt enable register – USER

R/W

—

Interrupt enable register – FPSC (unused for FPGAs)

—

Interrupt cause register

17-14

R/W

—

Readback address register (14 bits)

1B-18

—

Readback data register

1F-1C

R/W

—

Conﬁguration data register

23-20

—

Trap address register

27-24

—

Bus error address register

2B-28

—

Interrupt vector 1 predeﬁned by conﬁguration bit stream

2F-2C

—

Interrupt vector 2 predeﬁned by conﬁguration bit stream

33-30

—

Interrupt vector 3 predeﬁned by conﬁguration bit stream

37-34

—

Interrupt vector 4 predeﬁned by conﬁguration bit stream

3B-38

—

Interrupt vector 5 predeﬁned by conﬁguration bit stream

3F-3C

—

Interrupt vector 6 predeﬁned by conﬁguration bit stream

43—40

—

Top-left PPLL

47—44

—

Top-left HPLL

53—50

—

Top-right PPLL

63—60

—

Bottom-left PPLL

67—64

—

Bottom-left HPLL

73—70

—

Bottom-right PPLL

Byte

bit

Read/Write

Description

7-0

R/W

Interrupt Enable Register – MPI

7-0

R/W

Interrupt Enable Register – USER

7-0

R/W

Interrupt Enable Register – FPSC

Interrupt Cause Registers

USER_IRQ_GENERAL;

USER_IRQ_SLAVE;

USER_IRQ_MASTER;

CFG_IRQ_DATA;

ERR_FLAG 1

MPI_IRQ

FPSC_IRQ_SLAVE;

FPSC_IRQ_MASTER

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