OR4 datasheet(69/152 Pages) LATTICE

69 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

FPGA Conﬁguration Modes (continued)

5-9738(F).b

Figure 41. PowerPC/MPI Conﬁguration Schematic

Conﬁguration readback can also be performed via the MPI when it is in user mode. The MPI is enabled in user

mode by setting the MP_USER_ENABLE bit to 1 in the conﬁguration control register prior to the start of conﬁgura-

tion or through a conﬁguration option. To perform readback, the host processor writes the 14-bit readback start

address to the readback address registers and sets the SYS_RD_CFG bit to one, then back to zero in the conﬁgu-

ration control register. Readback data is returned 8 bits at a time to the readback data register and is valid when the

DATA_RDY bit of the status register is 1. There is no error checking during readback. A ﬂow chart of the MPI read-

back operation is shown in Figure 43. The RD_DATA pin used for dedicated FPGA readback is invalid during MPI

readback.

DOUT

CCLK

D[0:n]

PPC_A[14:31]

MPI_CLK

MPI_RW

MPI_ACK

MPI_BDIP

MPI_IRQ

MPI_STRB

CS0

CS1

HDC

LDC

D[0:n]

A[14:31]

CLKOUT

RD/WR

BDIP

IRQx

TO DAISY-

CHAINED

DEVICES

POWERPC

ORCA

8, 16, 32

FPGA

SERIES 4

DONE

INIT

BUS

CONTROLLER

DP[0:m]

1, 2, 4

MPI_BURST

BURST

MPI_TEA

TEA

MPI_RTRY

RETRY

MPI_TSZ[0:1]

TSZ[0:1]

OR4 Datasheet(PDF) 69 Page - Lattice Semiconductor

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