OR4 datasheet(56/152 Pages) LATTICE

56 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

FPGA States of Operation

Prior to becoming operational, the FPGA goes through

a sequence of states, including initialization, conﬁgura-

tion, and start-up. Figure 33 outlines these three states.

5-4529(F).

Figure 33. FPGA States of Operation

Initialization

Upon powerup, the device goes through an initialization

process. First, an internal power-on-reset circuit is trig-

gered when power is applied. When VDD15 and VDD33

reach the voltage at which portions of the FPGA begin

to operate, the I/Os are conﬁgured based on the conﬁg-

uration mode, as determined by the mode select inputs

M[3:0]. A time-out delay is then initiated to allow the

power supply voltage to stabilize. The INIT and DONE

outputs are low.

At the end of initialization, the default conﬁguration

option is that the conﬁguration RAM is written to a low

state. This prevents internal shorts prior to conﬁgura-

tion. As a conﬁguration option, after the ﬁrst conﬁgura-

tion (i.e., at reconﬁguration), the user can reconﬁgure

without clearing the internal conﬁguration RAM ﬁrst.

The active-low, open-drain initialization signal INIT is

released and must be pulled high by an external resis-

tor when initialization is complete. To synchronize the

conﬁguration of multiple FPGAs, one or more INIT pins

should be wire-ANDed. If INIT is held low by one or

more FPGAs or an external device, the FPGA remains

in the initialization state. INIT can be used to signal that

the FPGAs are not yet initialized. After INIT goes high

for two internal clock cycles, the mode lines (M[3:0])

are sampled, and the FPGA enters the conﬁguration

state.

The high during conﬁguration (HDC), low during conﬁg-

uration (LDC), and DONE signals are active outputs in

the FPGA’s initialization and conﬁguration states. HDC,

LDC

, and DONE can be used to provide control of

external logic signals such as reset, bus enable, or

PROM enable during conﬁguration. For parallel master

conﬁguration modes, these signals provide PROM

enable control and allow the data pins to be shared

with user logic signals.

If conﬁguration has begun, an assertion of RESET or

PRGM

initiates an abort, returning the FPGA to the ini-

tialization state. The PRGM and RESET pins must be

pulled back high before the FPGA will enter the conﬁg-

uration state. During the start-up and operating states,

only the assertion of PRGM causes a reconﬁguration.

In the master conﬁguration modes, the FPGA is the

source of conﬁguration clock (CCLK). In this mode, the

initialization state is extended to ensure that, in daisy-

chain operation, all daisy-chained slave devices are

ready. Independent of differences in clock rates, master

mode devices remain in the initialization state an addi-

tional six internal clock cycles after INIT goes high.

When conﬁguration is initiated, a counter in the FPGA

is set to 0 and begins to count conﬁguration clock

cycles applied to the FPGA. As each conﬁguration data

frame is supplied to the FPGA, it is internally assem-

bled into data words. Each data word is loaded into the

internal conﬁguration memory. The conﬁguration load-

ing process is complete when the internal length count

equals the loaded length count in the length count ﬁeld,

and the required end of conﬁguration frame is written.

During conﬁguration, the PIO and PLC latches/FFs are

held set/reset and the internal SLIC buffers are

3-stated. The combinatorial logic begins to function as

the FPGA is conﬁgured. Figure 34 shows the general

waveform of the initialization, conﬁguration, and start-

up states.

– ACTIVE I/O

– RELEASE INTERNAL RESET

– DONE GOES HIGH

START-UP

INITIALIZATION

CONFIGURATION

RESET

PRGM

LOW

PRGM

LOW

– CLEAR CONFIGURATION MEMORY

– INIT LOW, HDC HIGH, LDC LOW

OPERATION

POWERUP

– POWER-ON TIME DELAY

– M[3:0] MODE IS SELECTED

– CONFIGURATION DATA FRAME WRITTEN

– INIT HIGH, HDC HIGH, LDC LOW

– DOUT ACTIVE

YES

RESET,

INIT,

PRGM

LOW

BIT

ERROR

YES

OR4 Datasheet(PDF) 56 Page - Lattice Semiconductor

OR4 Datasheet(HTML) 56 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL