 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
OR4 Datasheet(PDF) 90 Page - Lattice Semiconductor |
|
|
|||||||||||||||||||||||||||||
OR4 Datasheet(HTML) 90 Page - Lattice Semiconductor |
|
|
90 / 152 page  90 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Timing Characteristics (continued) Table 52. Primary CLK (PCLK) Setup/Hold Time using on-chip PLLs (Pin-to-Pin) OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C Notes: 1. The pin-to-pin timing parameters in this table will match ispLEVER if the clock delay multiplier in the setup preference is set to 0.95 for setup time and 1.05 for hold time. 2. Timing uses the automatic delay compensation mode of the PLLs. The feedback to the PLL is provided by the global system clock routing. Other delay values are possible by using the phase modifications mode of the PLL instead. 3. This setup/hold time is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer delay, PLL block, the clock routing to the PIO CLK input, the setup/hold time of the PIO FF (with the data input delay disabled) and the LVTTL (3.3 V) input data buffer to PIO FF delay. The PCLK input clock is connected at the semi-dedicated PLL input pin. 4. Note that the PIO cycle stealing delay adjustments and the PLL cycle stealing delay adjustments are each attempting to pull the same clock in both directions. If both are being used, then the difference between them will provide the basis for PIO setup and hold times. 5. For timing improvements using other I/O buffer types for the input clock buffer or input data buffer, see Table 53. Description Device Speed Unit -1 -2 -3 Min Max Min Max Min Max Input to PCLK Setup Time, Input Data Delay Enabled OR4E02 OR4E04 OR4E06 7.92 8.01 8.08 — — — 7.48 7.56 7.62 — — — 6.81 6.88 6.94 — — — ns ns ns Input to PCLK Setup Time, No Input Data Delay OR4E02 OR4E04 OR4E06 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — ns ns ns Input to PCLK Hold Time, Input Data Delay Enabled OR4E02 OR4E04 OR4E06 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — 0.00 0.00 0.00 — — — ns ns ns Input to PCLK Hold Time, No Input Data Delay OR4E02 OR4E04 OR4E06 1.55 1.56 1.57 — — — 1.50 1.51 1.52 — — — 1.36 1.37 1.38 — — — ns ns ns Input Delay Adjustments from PIO Cycle Stealing (typically used to reduce setup time by the min value shown): One Delay Cell Two Delay Cells Three Delay Cells All All All — — — 0.89 1.64 2.43 — — — 0.70 1.29 1.98 — — — 0.64 1.18 1.80 ns ns ns PLL Delay Adjustments from Cycle Stealing (used to reduce hold by the min delay value shown): One Delay Cell Two Delay Cells Three Delay Cells All All All — — — 0.89 1.64 2.43 — — — 0.70 1.29 1.98 — — — 0.64 1.18 1.80 ns ns ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
