OR4 datasheet(78/152 Pages) LATTICE

78 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics

To define speed grades, the ORCA series part number designation (see Ordering Information) uses a single-digit

number to designate a speed grade. This number is not related to any single ac parameter. Higher numbers indi-

cate a faster set of timing parameters. The actual speed sorting is based on testing the delay in a path consisting of

an input buffer, combinatorial delay through all PLCs in a row, and an output buffer. Other tests are then done to

verify other delay parameters, such as routing delays, setup times to FFs, etc.

The most accurate timing characteristics are reported by the timing analyzer in ispLEVER™ design software. A

timing report provided by the development system after layout divides path delays into logic and routing delays.

The timing analyzer can also provide logic delays prior to layout. While this allows routing budget estimates, there

is wide variance in routing delays associated with different layouts.

The logic timing parameters noted in the Electrical Characteristics section of this data sheet are the same as those

in ispLEVER. In the timing tables that follow, symbol names are generally a concatenation of the PFU operating

mode (as defined in Table 3) and the parameter type. The setup, hold, and propagation delay parameters, defined

below, are designated in the symbol name by the SET, HLD, and DEL characters, respectively. The values given

for the parameters are the same as those used during production testing and speed binning of the devices. The

junction temperature and supply voltage used to characterize the devices are listed in the delay tables and the

delay values in this data sheet are from ispLEVER. Actual delays at nominal temperature and voltage for best-case

processes can be much better than the values given.

It should be noted that the junction temperature used in the tables is generally 85 °C or 100 °C, based on the tem-

perature grade of the device. The junction temperature for the FPGA depends on the power dissipated by the

device, the package thermal characteristics (ΘJA), and the ambient temperature, as calculated in the following

equation and as discussed further in the Package Thermal Characteristics section:

TJmax = TAmax + (P • ΘJA) °C

Note: The user must determine this junction temperature to see if the delays from ispLEVER should be derated

based on the following derating tables.

Table 37—Table 38 provide approximate power supply and junction temperature derating for Series 4 commercial

and industrial devices. The delay values in this data sheet and reported by ispLEVER are shown as 1.00 in the

tables. The method for determining the maximum junction temperature is defined in the Package Thermal Charac-

teristics section. Taken cumulatively, the range of parameter values for best-case vs. worst-case processing, sup-

ply voltage, and junction temperature can approach 3 to 1.

The typical timing path in Series 4 is made up of both 3.3 V (VDDIO and/or VDD33) components and 1.5 V (VDD15)

components. For example, all I/O circuits use VDDIO at the device interface but all internal routing and I/O register

logic use VDD15. Thus actual voltage derating needs to be done based on multiple parameters. A simple approxi-

mation is that 50% of the delay path is due to each of these parameters. All internal paths use VDD15 for logic and

VDD33 for routing, but if VDD33 remains above 3.0 V the internal delays can be assumed to be dependent on

VDD15 derating values only. Note however that temperature derating is approximately the same percentage for all

three supply voltages thus allowing one temperature derating value to be used. For the most accurate results, volt-

age and temperature derating capabilities to be released in ispLEVER should be used.

OR4 Datasheet(PDF) 78 Page - Lattice Semiconductor

OR4 Datasheet(HTML) 78 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL