OR4 datasheet(73/152 Pages) LATTICE

73 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

FPGA Conﬁguration Modes (continued)

5-4487(F).a

Figure 45. Slave Parallel Conﬁguration Schematic

Daisy-Chaining

Multiple FPGAs can be conﬁgured by using a daisy-chain of the FPGAs. Daisy-chaining uses a lead FPGA and one

or more FPGAs conﬁgured in slave serial mode. The lead FPGA can be conﬁgured in any mode except slave paral-

lel mode.

All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on

positive CCLK and out on positive CCLK edges.

An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received

the appropriate number of data frames so that downstream FPGAs do not receive frame start indications. After

loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its

conﬁguration data frames. The loading of conﬁguration data continues after the lead device has received its conﬁg-

uration data if its internal frame bit counter has not reached the length count. When the conﬁguration RAM is full

and the number of bits received is less than the length count ﬁeld, the FPGA shifts any additional data out on

DOUT.

The conﬁguration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the

positive edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain conﬁguration.

The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the conﬁg-

uration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an

internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode and MPI mode

device outputs eight CCLKs for each write cycle. If the lead device is conﬁgured in slave mode, CCLK must be

routed to the lead device and to all of the daisy-chained devices.

MICRO-

PROCESSOR

SYSTEM

D[7:0]

DONE

CCLK

CS1

HDC

LDC

VDD

INIT

PRGM

CS0

SERIES

FPGA

ORCA

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