OR4 datasheet(43/152 Pages) LATTICE

43 / 152 page

Data Sheet

May, 2006

Lattice Semiconductor

ORCA Series 4 FPGAs

Special Function Blocks (continued)

ISC_READ is similar to the ORCA RAM_Read instruction which allows the user to readback the conﬁguration RAM

contents serially out on TDO. Both must monitor the PDONE signal to determine weather or not conﬁguration is

completed. ISC_READ used a 1-bit register to synchronously readback data coming from the conﬁguration mem-

ory. The readback data is clocked into the ISC_READ data register and then clocked out TDO on the falling edge or

TCK.

Table 19. Series 4E Boundary-Scan Vendor-ID Codes

* PLC array size of FPGA, reverse bit order.

Note: Table assumes version 0.

Device

Version (4 bit)

Part* (10 bit)

Family (6 bit)

Manufacturer (11 bit)

LSB (1 bit)

OR4E02

0000

0011100000

001000

00000011101

OR4E04

0000

0001010000

001000

00000011101

OR4E06

0000

0000110000

001000

00000011101

ORCA Boundary-Scan Circuitry

The ORCA Series boundary-scan circuitry includes a

test access port controller (TAPC), instruction register

(IR), boundary-scan register (BSR), and bypass regis-

ter. It also includes circuitry to support the four pre-

deﬁned instructions.

Figure 27 shows a functional diagram of the boundary-

scan circuitry that is implemented in the ORCA Series.

The input pins’ (TMS, TCK, and TDI) locations vary

depending on the part, and the output pin is the dedi-

cated TDO/RD_DATA output pad. Test data in (TDI) is

the serial input data. Test mode select (TMS) controls

the boundary-scan test access port controller (TAPC).

Test clock (TCK) is the test clock on the board.

The BSR is a series connection of boundary-scan cells

(BSCs) around the periphery of the IC. Each I/O pad on

the FPGA, except for CCLK, DONE, and the boundary-

scan pins (TCK, TDI, TMS, and TDO), is included in the

BSR. The ﬁrst BSC in the BSR (connected to TDI) is

located in the ﬁrst PIO I/O pad on the left of the top side

of the FPGA (PTA PIO). The BSR proceeds clockwise

around the top, right, bottom, and left sides of the array.

The last BSC in the BSR (connected to TDO) is located

on the top of the left side of the array (PL1D).

The bypass instruction uses a single FF, which resyn-

chronizes test data that is not part of the current scan

operation. In a bypass instruction, test data received on

TDI is shifted out of the bypass register to TDO. Since

the BSR (which requires a two FF delay for each pad)

is bypassed, test throughput is increased when devices

that are not part of a test operation are bypassed.

The boundary-scan logic is enabled before and during

conﬁguration. After conﬁguration, a conﬁguration

option determines whether or not boundary-scan logic

is used.

The 32-bit boundary-scan identiﬁcation register con-

tains the manufacturer’s ID number, unique part num-

ber, and version (as described earlier). The

identiﬁcation register is the default source for data on

TDO after RESET if the TAP controller selects the shift-

data-register (SHIFT-DR) instruction. If boundary scan

is not used, TMS, TDI, and TCK become user I/Os, and

TDO is 3-stated or used in the readback operation.

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