OR4 datasheet(55/152 Pages) LATTICE

55 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Phase-Locked Loops (continued)

Table 29. STS-3/STM-1 PLL2 Speciﬁcations

All Series 4 PLLs operate from the VDD33 power supply. Care needs to be taken during board layout to properly iso-

late and ﬁlter this power supply. More information about the PLLs is available in the Series 4 FPGA PLL Elements

application note. The location of all eight PLLs on Series 4 FPGAs is shown in Figure 32 and Table 30.

0045(F)

Figure 32. PLL Naming Scheme

Table 30. Phase-lock Loops Index

Parameter

Min

Nom

Max

Unit

VDD15

1.425

1.5

1.575

VDD33

3.0

3.3

3.6

Operating Temp

–40

—

125

Input Clock Frequency

140

155.52

170

MHz

Output Clock Frequency

140

155.52

170

MHz

Input Duty Cycle Tolerance

—

Output Duty Cycle

Lock Time

—

<50

—

μs

Name

Description

[UL][LL][UR][LR]PPLL

Universal user programmable PLL (15—200 MHz)

[UL][LL]HPPLL

Universal user programmable PLL (60—420 MHz)

URPLL1

DS-1/E-1 dedicated PLL

LRPLL2

STS-1/STM-1 dedicated PLL

LRPPLL LRPLL2

LLPPLL LLHPPLL

URPPLL URPLL1

ULPPLL ULHPPLL

OR4 Datasheet(PDF) 55 Page - Lattice Semiconductor

OR4 Datasheet(HTML) 55 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL