OR4 datasheet(29/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Embedded Block RAM (continued)

0308(F)

Figure 21. EBR Read and Write Cycles with Write Through and Nonregistered Read Port

Table 9. FIFO Signals

Port Signals

I/O

Function

AR0[5:0]

Programs FIFO ﬂags. Used for partially empty ﬂag size.

AR1[9:0]

Programs FIFO ﬂags. Used for partially full ﬂag size.

Full Flag.

PFF

Partially Full Flag.

PEF

Partially Empty Flag.

Empty Flag.

D0[17:0]

Data inputs for all conﬁgurations.

D1[17:0]

Data inputs for 256x36 conﬁgurations only.

CKW[0:1]

Positive-edge write port clock. Port 1 only used for 256x36 conﬁgurations.

CKR[0:1]

Positive-edge read port clock. Port 1 only used for 256x36 conﬁgurations.

CSW[1:0]

Active-high write enable. Port 1 only used for 256x36 conﬁgurations.

CSR[1:0]

Active-high read enable. Port 1 only used for 256x36 conﬁgurations.

RESET

Active-low Resets FIFO pointers.

Q0[17:0]

Data outputs for all conﬁgurations.

Q1[17:0]

Data outputs for 256x36 conﬁgurations.

CKWPH

CKWPL

CSWSU

CSWH

AWH

DSU

BWSU

BWH

AWSU

CKWQ

AQH

CKW

CSW

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