OR4 datasheet(67/152 Pages) LATTICE

67 / 152 page

Data Sheet

May, 2006

Lattice Semiconductor

ORCA Series 4 FPGAs

FPGA Conﬁguration Modes (continued)

Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.

5-4456(F).a

Figure 39. Master Serial Conﬁguration Schematic

DIN

ORCA

SERIES

FPGA

CCLK

DOUT

TO DAISY-

CHAINED

DEVICES

DATA

CLK

CEO

DATA

CLK

RESET/OE

CEO

TO MORE

SERIAL ROMs

AS NEEDED

DONE

PRGM

PROGRAM

RESET/OE

Asynchronous Peripheral Mode

Figure 40 shows the connections needed for the asyn-

chronous peripheral mode. In this mode, the FPGA

system interface is similar to that of a microprocessor-

peripheral interface. The microprocessor generates the

control signals to write an 8-bit byte into the FPGA. The

FPGA control inputs include active-low CS0 and active-

high CS1 chip selects and WR and RD inputs. The chip

selects can be cycled or maintained at a static level

during the conﬁguration cycle. Each byte of data is writ-

ten into the FPGA’s D[7:0] input pins. D[7:0] of the

FPGA can be connected to D[7:0] of the microproces-

sor only if a standard prom ﬁle format is used. If a .bit

or .rbt ﬁle is used from ispLEVER, then the user must

mirror the bytes in the .bit or .rbt ﬁle OR leave the .bit or

.rbt ﬁle unchanged and connect D[7:0] of the FPGA to

D[0:7] of the microprocessor.

The FPGA provides an RDY/BUSY status output to indi-

cate that another byte can be loaded. A low on RDY/

BUSY

indicates that the double-buffered hold/shift reg-

isters are not ready to receive data, and this pin must

be monitored to go high before another byte of data

can be written. The shortest time RDY/BUSY is low

occurs when a byte is loaded into the hold register and

the shift register is empty, in which case the byte is

immediately transferred to the shift register. The long-

est time for RDY/BUSY to remain low occurs when a

byte is loaded into the holding register and the shift

conﬁguration RAM.

The RDY/BUSY status is also available on the D7 pin by

enabling the chip selects, setting WR high, and apply-

ing RD low, where the RD input provides an output

enable for the D[7:3] when RD is low. The D[2:0] pins

are not enabled to drive when RD is low and, therefore,

only act as input pins in asynchronous peripheral

mode. Optionally, the user can ignore the RDY/BUSY

status and simply wait until the maximum time it would

take for the RDY/BUSY line to go high, indicating the

FPGA is ready for more data, before writing the next

data byte.

The following signals are also available on D[6:3] when

is high and RD is low:

■

D[6:5] is a 2-bit conﬁguration bitstream error descrip-

tion ﬂag: 00= no error, 01 = ID error, 10 = checksum

error, 11 = stop bit/frame alignment error.

■

D[4:3] is a 2-bit system bus error ﬂag: 00 = no error,

01 = one error occurred, 11 = multiple errors

occurred.

One FPGA in asynchronous peripheral mode can pro-

vide conﬁguration data out on DOUT to additional

FPGAs in a daisy-chain conﬁguration. The conﬁgura-

tion data on DOUT is provided synchronously with the

rising edge of CCLK.

OR4 Datasheet(PDF) 67 Page - Lattice Semiconductor

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