SH7727 datasheet(53/1109 Pages) RENESAS

53 / 1109 page

Rev. 5.00 Dec 12, 2005 page liii of lxxii

Figures

Section 1 Overview and Pin Functions

Figure 1.1

Block Diagram .......................................................................................................

Figure 1.2

Pin Arrangement (PRQP0240KC-B) .....................................................................

Figure 1.3

Pin Arrangement (PLBG0240JA-A) ...................................................................... 10

Section 2 CPU

Figure 2.1

Figure 2.2

Figure 2.3

General Purpose Register (Not in DSP Mode)....................................................... 25

Figure 2.4

General Purpose Register (DSP Mode).................................................................. 26

Figure 2.5

Control Registers (1) .............................................................................................. 29

Figure 2.5

Control Registers (2) .............................................................................................. 30

Figure 2.6

System Registers .................................................................................................... 31

Figure 2.7

DSP Registers.........................................................................................................35

Figure 2.8

Connections of DSP Registers and Buses .............................................................. 37

Figure 2.9

Longword Operand ................................................................................................ 38

Figure 2.10 Data Format............................................................................................................ 39

Figure 2.11 Byte, Word, and Longword Alignment .................................................................. 40

Figure 2.12 X and Y Data Transfer Addressing ........................................................................ 49

Figure 2.13 Single Data Transfer Addressing............................................................................ 50

Figure 2.14 Modulo Addressing ................................................................................................ 52

Figure 2.15 DSP Instruction Formats ........................................................................................ 58

Figure 2.16 Sample Parallel Instruction Program...................................................................... 87

Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions .................... 95

Section 3 Memory Management Unit (MMU)

Figure 3.1

MMU Functions ..................................................................................................... 99

Figure 3.2

Logical Address Space Mapping............................................................................ 101

Figure 3.3

MMU Register Contents ........................................................................................ 104

Figure 3.4

Overall Configuration of the TLB.......................................................................... 105

Figure 3.5

Logical Address and TLB Structure....................................................................... 106

Figure 3.6

TLB Indexing (IX = 1) ........................................................................................... 107

Figure 3.7

TLB Indexing (IX = 0) ........................................................................................... 108

Figure 3.8

Objects of Address Comparison............................................................................. 109

Figure 3.9

Operation of LDTLB Instruction............................................................................ 113

Figure 3.10 Synonym Problem .................................................................................................. 115

Figure 3.11 MMU Exception Generation Flowchart ................................................................. 120

Figure 3.12 MMU Exception Signals in Instruction Fetch........................................................ 121

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