SH7727 datasheet(57/1109 Pages) RENESAS

57 / 1109 page

Rev. 5.00 Dec 12, 2005 page lvii of lxxii

Figure 14.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access:

4 Cycles)................................................................................................................. 422

Figure 14.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles,

DREQ Input Delayed)... 423

Figure 14.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) ........................................ 424

Figure 14.22 Burst Mode, Level Input ........................................................................................ 425

Figure 14.23 Burst Mode, Edge Input ......................................................................................... 426

Figure 14.24 Source Address Reload Function Diagram............................................................. 427

Figure 14.25 Timing Chart of Source Address Reload Function................................................. 428

Figure 14.26 CMT Block Diagram.............................................................................................. 431

Figure 14.27 Counter Operation .................................................................................................. 435

Figure 14.28 Count Timing ......................................................................................................... 436

Figure 14.29 Timing of CMF Setting .......................................................................................... 437

Figure 14.30 Timing of CMF Clear by the CPU ......................................................................... 437

Section 15 Timer (TMU)

Figure 15.1 TMU Block Diagram.............................................................................................. 444

Figure 15.2 Setting the Count Operation ................................................................................... 451

Figure 15.3 Auto-Reload Counter Operation............................................................................. 452

Figure 15.4 Count Timing when Internal Clock is Operating ................................................... 452

Figure 15.5 Count Timing when On-Chip RTC Clock is Operating ......................................... 453

Figure 15.6 UNF Set Timing ..................................................................................................... 453

Figure 15.7 Status Flag Clear Timing........................................................................................ 454

Section 16 Realtime Clock (RTC)

Figure 16.1 RTC Block Diagram............................................................................................... 458

Figure 16.2(a) Setting the Time ................................................................................................. 474

Figure 16.2(b) Setting the Time................................................................................................. 474

Figure 16.3 Reading the Time ................................................................................................... 475

Figure 16.4 Using the Alarm Function ...................................................................................... 476

Figure 16.5 Example of Crystal Oscillator Circuit Connection................................................. 477

Figure 16.6 Periodic Interrupt Function Setting ........................................................................ 478

Section 17

Serial Communication Interface (SCI)

Figure 17.1 SCI Block Diagram ................................................................................................ 482

Figure 17.2 SCPT[1]/SCK0 Pin ................................................................................................ 483

Figure 17.3 SCPT[0]/TxD0 Pin................................................................................................. 484

Figure 17.4 SCPT[0]/RxD0 Pin................................................................................................. 485

Figure 17.5 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)................................................. 511

Figure 17.6 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode)............................................................................................ 513

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