SH7727 datasheet(19/1109 Pages) RENESAS

19 / 1109 page

Rev. 5.00 Dec 12, 2005 page xix of lxxii

Page

Previous Version

Revised Version

608

20.2.2 Clock Select Register (SISCR)

• Bit 15Master Clock Source Choice

(MSSEL):

Use PCLK as master clock

Use Peripheral clock (P

φ) as master clock

628

Figure 20.2 Serial Clock Supply System

BRG

SIOMCLK

P_CLK

BRG

SIOMCLK

Peripheral clock

φ)

635

20.3.5 Control Data Interface

(1) Control by Slot Positions (Master Mode

Note: When using this method, PCLK

should be used as the master clock (Master

Clock Select (MSSEL) = 1).

Note: When using this method, Peripheral

clock should be used as master clock

(Master Clock Select (MSSEL) = 1).

651

20.4 Usage Notes

Item 7, 8, added

679

22.1.2 Pin Configuration

Table 22.1 Pin Configuration (Digital

Transceiver Signal)

Name

Symbol

I/O

Description

TXDPLS pin

USB1d_TXDPLS

Output

+ transmit output pin

TXDMNS pin

USB1d_TXDMNS

Output

− transmit output pin

TXENL pin

USB1d_TXENL

Output

Driver output enable pin

Name

Symbol

I/O

Description

TXDPLS pin

USB1d_TXDPLS

Output

+ transmit output pin

TXENL pin

USB1d_TXENL

Output

Driver output enable pin

709

23.6.3 Control Transfer

Figure 23.8 Status Stage Operation

(Control-In)

Replaced

720

23.9 Usage Notes

Newly added

758

24.7 Notes on Using USB Host with

Versions Previous to the SH7727C

Newly added

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