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SH7727 Datasheet(PDF) 18 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 1109 page  Rev. 5.00 Dec 12, 2005 page xviii of lxxii Page Previous Version Revised Version 563 19.1.1 Features • On-chip modem control functions ( RTS and CTS) • On-chip modem control functions ( RTS2 and CTS2) 564 Figure 19.1 SCIF Block Diagram RxD2 TxD2 SCIF SCBRR2 SCSSR2 SCSCR2 SCFTDR2 SCTSR2 SCFRDR2 (16stages) (16stages) SCRSR2 SCSMR2 SCFDR2 SCFCR2 SCPCR2 SCFDR2 Parity generation Parity check Clock Module data bus Internal data bus P φ P φ/4 P φ/16 P φ/64 TXI ERI BRI BRI Baud rate generator Transmit/ receive control RxD2 TxD2 RTS2 CTS2 SCIF SCBRR2 SCSSR2 SCSCR2 SCFTDR2 SCTSR2 SCFRDR2 (16stages) (16stages) SCRSR2 SCSMR2 SCFDR2 SCFCR2 SCPCR2 SCFDR2 Parity generation Parity check Clock Module data bus Internal data bus P φ P φ/4 P φ/16 P φ/64 TXI ERI BRI BRI Baud rate generator Transmit/ receive control 565 19.1.2 Block Diagram Figures 19.2 and 19.3 show SCIF I/O ports. Bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR control an input/output and data of the SCIF pins. … Figure 19.2 and 19.3 show SCIF I/O ports. Bits 15, 14, 9, 8 of SCPCR and bits 7 and 4 of SCPDR control an input/output and data of the SCIF pins. … 603 20.1.1 Features • Serial clock External clock or internal clock (P_CLK) are able to be used as clock source. External clock or peripheral clock (Pφ) are able to be used as clock source. 604 20.1.2 Block Diagram Figure 20.1 SIOF Block Diagram Control register 16 32 Tx_FIFO 32 bits × 16 stages Bus I/F RXD_SIO TXD_SIO SCK_SIO SIOFSYNC 32 32 32 PP-BUS Rx_FIFO 32 bits × 16 stages S/P Rx control data 32 32 Timing control SIOMCLK Baud rate generator P/S Tx control data 1/n MCLK Control register 16 32 Tx_FIFO 32 bits × 16 stages Bus I/F RXD_SIO TXD_SIO SCK_SIO SIOFSYNC 32 32 32 Peripheral bus Rx_FIFO 32 bits × 16 stages S/P Rx control data 32 32 Timing control SIOMCLK Baud rate generator P/S Tx control data 1/n MCLK SIOF |
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