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SH7727 Datasheet(PDF) 26 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 26 Page - Renesas Technology Corp |
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26 / 1109 page  Rev. 5.00 Dec 12, 2005 page xxvi of lxxii Page Previous Version Revised Version 942 Table 32.6 Control Signal Timing 33 MHz* 2 66.67 MHz* 3 Min Max Min Max RESETP pulse width tRESPW 20 — 20* 4 — RESETP setup time* 1 tRESPS 23 — 23 — RESETP hold time tRESPH 2 — 2 — RESETM pulse width tRESMW 12 — 12* 5 — RESETM setup time tRESMS 3 — 3 — RESETM hold time tRESMH 34 — 34 — BREQ setup time tBREQS 10 — 10 — BREQ hold time tBREQH 3 — 3 — NMI setup time * 1 tNMIS 10 — 10 — NMI hold time tNMIH 4 — 4 — IRQ5–IRQ0 setup time * 1 tIRQS 10 — 10 — IRQ5–IRQ0 hold time tIRQH 4 — 4 — BACK delay time tBACKD — 10 — 10 STATUS1, STATUS0 delay time tSTD — 16 — 16 Bus tri-state delay time 1 tBOFF1 015 0 15 Bus tri-state delay time 2 tBOFF2 015 0 15 Bus buffer-on time 1 tBON1 015 0 15 Bus buffer-on time 2 tBON2 015 0 15 Table 32.9 Control Signal Timing Min Max RESETP pulse width tRESPW 20* 2 — RESETP setup time* 1 tRESPS 23 — RESETP hold time tRESPH 2 — RESETM pulse width tRESMW 12* 3 — RESETM setup time tRESMS 3 — RESETM hold time tRESMH 34 — BREQ setup time tBREQS 10 — BREQ hold time tBREQH 3 — NMI setup time * 1 tNMIS 10 — NMI hold time tNMIH 4 — IRQ5–IRQ0 setup time * 1 tIRQS 10 — IRQ5–IRQ0 hold time tIRQH 4 — BACK delay time tBACKD — 10 STATUS1, STATUS0 delay time tSTD — 16 Bus tri-state delay time 1 tBOFF1 0 15 Bus tri-state delay time 2 tBOFF2 0 15 Bus buffer-on time 1 tBON1 0 15 Bus buffer-on time 2 tBON2 0 15 Notes: *1 RESETP, NMI and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock falls. When using as IRL, please observe the setup time. *2 When Vcc = 1.6 to 2.05 V and VccQ = 2.6 to 3.6 V, the upper limit of the external bus clock is 33 MHz. *3 When Vcc = 1.75 to 2.05 V and VccQ = 3.0 to 3.6 V, the upper limit of the external bus clock is 66.67 MHz. *4 In the standby mode, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100 µs). When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 µs). 1. RESETP, NMI and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock falls. When using as IRL, please observe the setup time. 2. In the standby mode, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100 µs). When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 µs). |
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