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SH7727 Datasheet(PDF) 33 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 33 Page - Renesas Technology Corp |
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33 / 1109 page ![]() Rev. 5.00 Dec 12, 2005 page xxxiii of lxxii Contents Section 1 Overview and Pin Functions ......................................................................... 1 1.1 Features ............................................................................................................................. 1 1.2 Block Diagram .................................................................................................................. 8 1.3 Pin Description.................................................................................................................. 9 1.3.1 Pin Arrangement .................................................................................................. 9 1.3.2 Pin Functions ....................................................................................................... 11 Section 2 CPU ...................................................................................................................... 21 2.1 Registers............................................................................................................................ 21 2.1.1 General Purpose Registers ................................................................................... 25 2.1.2 Control Registers ................................................................................................. 27 2.1.3 System Registers.................................................................................................. 31 2.1.4 DSP Registers ...................................................................................................... 31 2.2 Data Format ...................................................................................................................... 38 2.2.1 Data Format in Registers (Non-DSP Type) ......................................................... 38 2.2.2 DSP-Type Data Format........................................................................................ 38 2.2.3 Data Format in Memory....................................................................................... 40 2.3 Features of CPU Core Instructions.................................................................................... 40 2.4 Instruction Formats ........................................................................................................... 44 2.4.1 CPU Instruction Addressing Modes..................................................................... 44 2.4.2 DSP Data Addressing .......................................................................................... 48 2.4.3 CPU Instruction Formats ..................................................................................... 54 2.4.4 DSP Instruction Formats...................................................................................... 58 2.5 Instruction Set ................................................................................................................... 64 2.5.1 CPU Instruction Set ............................................................................................. 64 2.6 DSP Extended-Function Instructions ................................................................................ 79 2.6.1 Introduction.......................................................................................................... 79 2.6.2 Added CPU System Control Instructions............................................................. 80 2.6.3 Single and Double Data Transfer for DSP Data Instructions............................... 82 2.6.4 DSP Operation Instruction Set............................................................................. 85 Section 3 Memory Management Unit (MMU) ........................................................... 97 3.1 Overview........................................................................................................................... 97 3.1.1 Features................................................................................................................ 97 3.1.2 Role of MMU....................................................................................................... 97 3.1.3 SH7727 MMU ..................................................................................................... 99 3.1.4 Register Configuration......................................................................................... 103 3.2 Register Description.......................................................................................................... 103 |
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