SH7727 datasheet(9/1109 Pages) RENESAS

9 / 1109 page

Rev. 5.00 Dec 12, 2005 page ix of lxxii

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188

7.3.7 Interrupt Request Register 0 (IRR0)

The IRR0 is an 8-bit register that indicates

interrupt requests from external input pins

IRQ0 to IRQ5 and PINT0 to PINT15. This

reset or manual reset, but is not initialized

in standby mode.

When using edge sensing for IRQ

interrupts, do the following to clear IR0.

To clear bits IRQ5R to IRQ0R to 0, read

from IRR0 before writing. After confirming

that the bits to be cleared to 0 are set to 1,

write 0 to them. In this case write 0 only to

the bits to be cleared; write 1 to the other

bits. The values of the bits to which 1 is

written do not change.

When level sensing is used for IRQ

interrupts, bits IRQ5R to IRQ0R indicate

whether or not an interrupt request has

been input. They can be set and cleared by

the values input to pins IRQ5R to IRQ0R

alone.

198

Figure 7.3 Interrupt Operation Flowchart

Yes

NMI?

Set interrupt cause in

INTEVT, INTEVT2

IRQOUT = low

Yes

NMI?

Set interrupt cause in

INTEVT, INTEVT2

199

7.4.2 Multiple Interrupts

When these procedures are followed in

order, an interrupt of higher priority than the

one being handled can be accepted after

clearing BL in step 4. Figure 7.3 shows a

sample interrupt operation flowchart.

When these procedures are followed in

order, an interrupt of higher priority than the

one being handled can be accepted after

clearing BL in step 4.

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