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SH7727 Datasheet(PDF) 20 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 20 Page - Renesas Technology Corp |
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20 / 1109 page  Rev. 5.00 Dec 12, 2005 page xx of lxxii Page Previous Version Revised Version 759 25.1.1 Features • Supports 1/2/4/8/15/16-bpp (bit per pixel) color modes • Supports 1/2/4-bpp grayscale modes • Supports 4/8/15/16-bpp (bit per pixel) color modes • Supports 1/2/4/6-bpp grayscale modes 760 Figure 25.1 Block Diagram CKIO P clock Bus clock (B φ) Peripheral clock (P φ) 762 Table 25.2 Register Configuration H'F606 H'F60F 763 25.2.1 LCDC Input Clock Register (LDICKR) This LCDC can select CKIO (bus clock), the P clock, or the external clock as its operation clock source. … This LCDC can select the bus clock (B φ), the peripheral clock (P φ), or the external clock as its operation clock source. … Bits 13, and 12 Input Clock Select (ICKSEL1 and ICKSEL0): CKIO is selected P clock is selected Bus clock (B φ) is selected Peripheral clock (P φ) is selected 766 25.2.2 LCDC Module Type Register (LDMTR) Bits 5 to 0—Module Interface Type Select (MIFTYP5 to MIFTYP0): If an STN or DSTN panel is selected, display control is performed using a 24-bit space-modulation FRC consisting of the 8- bit R, G, and B included in the LCDC, … If an STN or DSTN panel is selected, display control is performed using a 24-bit space-modulation FRC (Frame Rate Controller) consisting of the 8-bit R, G, and B included in the LCDC, … 783 25.2.17 LCDC Power Management Mode Register (LDPMMR) Bit 4 DON Pin Enable (DONE): Bit 4 DONE Description 0 Disabled: DON pin is masked and fixed low (Initial value) 1 Enabled: DON pin output is asserted and negated according to the power-on or power- off sequence Bit 4 DONE Description 0 Disabled: DON pin is masked and fixed lo w 1 Enabled: DON pin output is asserted and negated according to the power-on or power- off sequence (Initial value) 784 25.2.18 LCDC Power-Supply Sequence Period Register (LDPSPR) Bit: 15 14 13 12 11 10 98 765 432 10 ONA3 ONA2 ONA1 ONA0 ONB3 ONB2 ONB1 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 987654321 0 ONA3 ONA2 ONA1 ONA0 ONB3 ONB2 ONB1 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0 Initial value: 1 1 1 10 1 10000 0 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W |
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