SH7727 datasheet(12/1109 Pages) RENESAS

12 / 1109 page

Rev. 5.00 Dec 12, 2005 page xii of lxxii

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Previous Version

Revised Version

279

11.1.1 EXCPG

The extend clock pulse generator (EXCPG)

generates a divided clock from the CPU

clock (I

φ), the bus clock (Bφ), or the

external clock (UCLK).

The extend clock pulse generator (EXCPG)

generates a divided clock from the internal

clock (I

φ), the bus clock (Bφ), or the

external clock (UCLK).

Figure 11.1 Block Diagram of EXCPG

1/1

Select

USB clock

(48 MHz)

1/2

1/3

USB

host

USB

function

P clock

I clock

Bus clock

UCLK

1/1

Select

USB clock

(48 MHz)

1/2

1/3

USB

host

USB

function

Peripheral clock (P

φ)

Internal clock (I

φ)

Bus clock (B

φ)

External clock (UCLK)

281

11.3.1 EXCPG Control Register

(EXCPGCR)

Bits 5 to 3—Clock Select (USBCKSEL2 to

USBCKSEL0):

Bits 5 to 3

Function (Clock Selection)

110

External clock

Bits 5 to 3

Function (Clock Selection)

110

External clock (UCLK)

Bits 2 to 0 Function (Dividing Ratio

Selection):

Bits 2 to 0

Function (Dividing Ratio Selection)

1**

φ, CKIO, UCLK halted

Note:

To reduce power consumption, set USBDIVSEL2 to 1 and halts Iø, CKIO, or UCLK input.

Bits 2 to 0

Function (Dividing Ratio Selection)

1**

Internal clock (I

φ), bus clock (Bφ), external clock (UCLK) halted

Note:

To reduce power consumption, set USBDIVSEL2 to 1 and halts internal clock (I

φ), bus clock

φ), or external clock (UCLK) input.

281

11.4 Usage Notes

Newly added

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