SH7727 datasheet(62/1109 Pages) RENESAS

62 / 1109 page

Rev. 5.00 Dec 12, 2005 page lxii of lxxii

Figure 30.2 Continuous 32-MB Area Mode.............................................................................. 889

Figure 30.3 Continuous 16-MB Area Mode (Area 6)................................................................ 890

Figure 30.4 SH7727 Interface.................................................................................................... 903

Figure 30.5 PCMCIA Memory Card Interface Basic Timing.................................................... 907

Figure 30.6 PCMCIA Memory Card Interface Wait Timing..................................................... 908

Figure 30.7 PCMCIA I/O Card Interface Basic Timing............................................................ 909

Figure 30.8 PCMCIA I/O Card Interface Wait Timing ............................................................. 910

Figure 30.9 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 911

Section 31 User-Debugging Interface (H-UDI)

Figure 31.1 H-UDI Block Diagram ........................................................................................... 916

Figure 31.2 TAP Controller State Transitions ........................................................................... 925

Figure 31.3 H-UDI Reset........................................................................................................... 927

Section 32 Electrical Characteristics

Figure 32.1 Power-On Sequence ............................................................................................... 930

Figure 32.2 Power Supply Voltage and Operating Frequency .................................................. 935

Figure 32.3 EXTAL Clock Input Timing .................................................................................. 941

Figure 32.4 CKIO Clock Input Timing ..................................................................................... 941

Figure 32.5 CKIO Clock Output Timing................................................................................... 942

Figure 32.6 Power-on Oscillation Settling Time ....................................................................... 942

Figure 32.7 Oscillation Settling Time at Standby Return (Return by Reset)............................. 943

Figure 32.8 Oscillation Settling Time at Standby Return (Return by NMI).............................. 943

Figure 32.9 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0).............. 944

Figure 32.10 PLL Synchronization Settling Time by Reset or NMI Interrupt ............................ 944

Figure 32.11 PLL Synchronization Settling Time by IRQ/IRL and PINT0/1 Interrupt .............. 945

Figure 32.12 PLL Sync Stabilization Time at Frequency Multiplier Factor Change .................. 945

Figure 32.13 Reset Input Timing................................................................................................. 947

Figure 32.14 Interrupt signal Input Timing ................................................................................. 947

Figure 32.15 Bus Release Timing................................................................................................ 948

Figure 32.16 Pin Drive Timing at Standby.................................................................................. 948

Figure 32.17 Basic Bus Cycle (No Wait) .................................................................................... 951

Figure 32.18 Basic Bus Cycle (One Wait)................................................................................... 952

Figure 32.19 Basic Bus Cycle (External Wait, WAITSEL = 1) .................................................. 953

Figure 32.20 Burst ROM Bus Cycle (No Wait) .......................................................................... 954

Figure 32.21 Burst ROM Bus Cycle (Two Waits) ...................................................................... 955

Figure 32.22 Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ........................................ 956

Figure 32.23 Synchronous DRAM Read Bus Cycle (RCD

= 0, CAS Latency = 1, TPC = 0) .... 957

Figure 32.24 Synchronous DRAM Read Bus Cycle (RCD

= 2, CAS Latency = 2, TPC = 1) .... 958

Figure 32.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read

× 4),

RCD

= 0, CAS Latency = 1, TPC = 1)................................................................... 959

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