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SH7727 Datasheet(PDF) 27 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 27 Page - Renesas Technology Corp |
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27 / 1109 page  Rev. 5.00 Dec 12, 2005 page xxvii of lxxii Page Previous Version Revised Version 945, 946 Table 32.7 Bus Timing 33 MHz* 1 66.67 MHz* 2 Item Symbol Min Max Min Max Unit Address delay time tAD 1.5 16 1.5 13 ns Address setup time tAS 0 — 0 — ns Address hold time tAH* 3 7 — 7 — ns BS delay time tBSD — 12 — 12 ns CS delay time 1 tCSD1 1.5 12 1.5 12 ns CS delay time 2 tCSD2 1 12 1 12 ns Read/write delay time tRWD 1.5 10 1.5 10 ns Read/write hold time tRWH 0 — 0 — ns Read strobe delay time tRSD — 10 — 10 ns Read data setup time 1 tRDS1 6 — 6 — ns Read data setup time 2 tRDS2 7 — 7 — ns Read data hold time 1 tRDH1* 4 0 — 0 — ns Read data hold time 2 tRDH2 2 — 2 — ns Write enable delay time tWED 1 10 1 10 ns Write data delay time 1 tWDD1 — 14 — 14 ns Write data delay time 2 tWDD2 — 13 — 13 ns Table 32.10 Bus Timing Item Symbol Min Max Unit Conditions Address delay time tAD 1.5 13 ns Vcc = 1.70 to 2.05 V VccQ = 3.0 to 3.6 V 1.5 16 Other than the above Address setup time tAS 0 — ns Address hold time tAH* 1 7 — ns BS delay time tBSD — 12 ns CS delay time 1 tCSD1 1.5 12 ns CS delay time 2 tCSD2 1 12 ns Read/write delay time tRWD 1.5 10 ns Read/write hold time tRWH 0 — ns Read strobe delay time tRSD — 10 ns Read data setup time 1 tRDS1 6 — ns Read data setup time 2 tRDS2 7 — ns Read data hold time 1 tRDH1* 2 0 — ns Read data hold time 2 tRDH2 2 — ns Write enable delay time tWED 1 10 ns Write data delay time 1 tWDD1 — 14 ns Write data delay time 2 tWDD2 — 13 ns 33 MHz* 1 66.67 MHz* 2 Item Symbol Min Max Min Max Unit Write data hold time 1 tWDH1 1.5 — 1.5 — ns Write data hold time 2 tWDH2 1.5 — 1.5 — ns Write data hold time 3 tWDH3 2 — 2 — ns Write data hold time 4 tWDH4 2 — 2 — ns WAIT setup time tWTS 6 — 5 — ns WAIT hold time tWTH 0 — 0 — ns RAS delay time 2 tRASD2 1.5 12 1.5 12 ns CAS delay time 2 tCASD2 1.5 12 1.5 12 ns DQM delay time tDQMD 1.5 10 1.5 10 ns CKE delay time tCKED 1.5 12 1.5 12 ns ICIORD delay time tICRSD — 12 — 12 ns ICIOWR delay time tICWSD — 12 — 12 ns IOIS16 setup time tIO16S 12 — 12 — ns IOIS16 hold time tIO16H 4 — 4 — ns DACK delay time 1 tDAKD1 — 10 — 10 ns Item Symbol Min Max Unit Conditions Write data hold time 1 tWDH1 1.5 — ns Write data hold time 2 tWDH2 1.5 — ns Write data hold time 3 tWDH3 2 — ns Write data hold time 4 tWDH4 2 — ns WAIT setup time tWTS 5 — ns Vcc = 1.70 to 2.05 V VccQ = 3.0 to 3.6 V 6 — Other than the above WAIT hold time tWTH 0 — ns RAS delay time 2 tRASD2 1.5 12 ns CAS delay time 2 tCASD2 1.5 12 ns DQM delay time tDQMD 1.5 10 ns CKE delay time tCKED 1.5 12 ns ICIORD delay time tICRSD — 12 ns ICIOWR delay time tICWSD — 12 ns IOIS16 setup time tIO16S 12 — ns IOIS16 hold time tIO16H 4 — ns DACK delay time 1 tDAKD1 — 10 ns Notes: *1 When Vcc = 1.6 to 2.05 V and VccQ =2.6 to 3.6 V, the upper limit of the external bus clock is 33 MHz. *2 When Vcc = 1.75 to 2.05 V and VccQ = 3.0 to 3.6 V, the upper limit of the external bus clock is 66.67 MHz. *3 tAH: This is to deal with the latest negate timing of CSn, RD, or WEn. *4 tRDH1: This is to deal with the earliest negate timing of CSn or RD. 1. tAH: This is to deal with the latest negate timing of CSn, RD, or WEn. 2. tRDH1: This is to deal with the earliest negate timing of CSn or RD. |
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