SH7727 datasheet(10/1109 Pages) RENESAS

10 / 1109 page

Rev. 5.00 Dec 12, 2005 page x of lxxii

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234

Table 9.1 Power-Down Modes

Mode

Transition

Conditions

Sleep

mode

Execute

SLEEP

instruction

with STBY bit

cleared to 0

in STBCR

Module

standby

function

Set MSTP bit

of STBCR

to 1

Mode

Transition

Conditions

Sleep

mode

Execute

SLEEP

instruction

with STBY bit

cleared to 0

in STBCR

Module

standby

function

Set MSTP bit

of STBCR

to 1

Note 6, 7, added

Section 10.1.2 “Clock Abbreviation” deleted

259

Figure 10.1 Block Diagram of Clock Pulse

Generator

CAP1

CKIO2

CKIO

Cycle = Bcyc

CAP2

XTAL

EXTAL

PLL circuit 1

(

× 1, 2, 3, 4, 6)

Divider 1

Internal

clock (I

φ)

Cycle = Icyc

Peripheral

clock (P

φ)

Cycle = Pcyc

Divider 2

Clock pulse generator

PLL circuit 2

(

× 1, 4)

Crystal

oscillator

× 1

× 1/2

× 1/3

×1/4

× 1

× 1/2

× 1/3

× 1/4

× 1/6

Bus clock (P

φ)

Cycle = Bcyc

CAP1

CKIO2

CKIO

Cycle = Bcyc

CAP2

XTAL

EXTAL

PLL circuit 1

(

× 1, 2, 3, 4, 6)

Divider 1

Internal

clock (I

φ)

Cycle = Icyc

Peripheral

clock (P

φ)

Cycle = Pcyc

Divider 2

Clock pulse generator

PLL circuit 2

(

× 1, 4)

Crystal

oscillator

× 1

× 1/2

× 1/3

×1/4

× 1

× 1/2

× 1/3

× 1/4

× 1/6

Bus clock (P

φ)

Cycle = Bcyc

260

10.2.1 CPG Block Diagram

1. PLL Circuit 1

PLL circuit 1 doubles, triples, quadruples,

sextuples, or leaves unchanged the input

clock frequency from the CKIO terminal. ...

PLL circuit 1 doubles, triples, quadruples

sextuples, or leaves unchanged the input

clock frequency from the CKIO pin or PLL

circuit 2. …

SH7727 Datasheet(PDF) 10 Page - Renesas Technology Corp

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