SH7727 datasheet(77/1109 Pages) RENESAS

77 / 1109 page

Section 1 Overview and Pin Functions

Rev. 5.00 Dec 12, 2005 page 5 of 1034

REJ09B0254-0500

Item

Features

Bus state

controller (BSC)

• Physical address space divided into six areas (area 0, areas 2 to 6), each of

up to 64 Mbytes, with the following features settable for each area:

 Bus size (8, 16, or 32 bits)

 Number of wait cycles (hardware wait function also waited)

 Direct connection of SRAM, synchronous DRAM, and burst ROM

possible by designating memory to be connected to each area

 Supports PCMCIA interface (2 channels)

 Chip select signals (CS0, CS2–CS6) for relevant area

• Synchronous DRAM refresh function

 Programmable refresh interval

 Supports CAS-before-RAS refresh and self-refresh modes

 Supports power-down DRAM

• Synchronous DRAM burst access function

• Big endian or little endian can be specified

Li bus state

controller (LBSC)

• Bus State Controller for LCDC or USB Host

• Supports synchronous DRAM

• Synchronous DRAM access function (area 3)

User debug

Interface (H-UDI)

• E10A emulator support

• Pin arrangement conforming to JTAG specification

• Realtime branch trace

Timer (TMU)

• 3-channel auto-reload-type 32-bit timer

• Choice of six counter input clocks

• Maximum resolution: 2 MHz

Realtime clock

(RTC)

• Built-in clock, calendar functions, and alarm functions

• On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle

interrupt) of 1/256 second

Serial communi-

cation interface

(SCI)

• Asynchronous mode or clock synchronous mode can be selected

• Full-duplex communication

• Supports smart card interface

SH7727 Datasheet(PDF) 77 Page - Renesas Technology Corp

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