HD6433713 datasheet(184/324 Pages) RENESAS

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9.3 Operation

When using the 14-bit PWM, set the registers in the following sequence.

Set bit PWM in port mode register 2 (PMR2) to 1 so that pin P90/PWM is designated for

PWM output.

Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either

32768/

φ (PWCR0 = 1) or 16384/φ (PWCR0 = 0).

Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write

in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the

data in these registers will be latched in the PWM waveform generator, updating PWM

waveform generation in synchronization with internal signals.

One conversion period consists of 64 pulses, as shown in figure 9-2. The total of the high-

level pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL.

This relation can be represented as follows.

TH = (data value in PWDRU and PWDRL + 64) × tφ/2

where t

φ is the PWM input clock period, either 2/φ (bit PWCR0 = 0) or 4/φ (bit PWCR0 = 1).

If the data value in PWDRU and PWDRL is between H'3FC0 and H'3FFF, the PWM

output level will be high.

When the data value is H'0000, TH = 64 × tφ/2 = 32 tφ.

Example: Settings in order to obtain a conversion period of 8,192 µs:

When bit PWCR0 = 0, the conversion period is 16384/

φ, so φ must be 2 MHz. In

this case tfn = 128 µs, with 1/φ (resolution) = 0.5 µs.

When bit PWCR0 = 1, the conversion period is 32768/

φ, so φ must be 4 MHz. In

this case tfn = 128 µs, with 2/φ (resolution) = 0.5 µs.

Accordingly, for a conversion period of 8,192 µs, the system clock frequency (

φ)

must be 2 MHz or 4 MHz.

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HD6433713 Datasheet(PDF) 184 Page - Renesas Technology Corp