HD6433713 datasheet(323/324 Pages) RENESAS

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Appendix F Rise Time and Fall Time of High-Voltage Pins

With the mask ROM versions there is a choice of high-voltage pin output configurations. Either

PMOS open-drain (D) or MOS pull-down (E) may be selected. (Only PMOS open-drain is

available as the output configuration of high-voltage pins on ZTAT™ versions.)

The rise time tr and fall time tf of high-voltage pin output are as follows.

It is possible to estimate tr and tf from the time constant τ = C.R (time up to 63% of rise or fall).

tr: The time constant is determined by the PMOS on-resistance and load capacitance. The DC

on-resistance is approximately 200

Ω (based on V

OH = VCC – 3 V at –IOH = 15 mA,

3/0.015 = 200). The AC on-resistance however, includes the non-saturation state when the

PMOS transistor turns on (it is not a constant-current source), resulting in a longer time

constant. Assuming a load capacitance of 30 pF at high-voltage pins, the minimum value is

approximately 20 ns.

tf: The time constant is determined by the pull-down resistance and load capacitance (including

wiring capacitance, etc.). As an example, assuming a pull-down resistance of 5 k

Ω and load

capacitance of 30 pF, the following is derived.

tf ≥ 5 × 103 × 30 × 10–12 = 150 × 10–9 (150 ns)

MOS pull-down resistance varies from 45 k

Ω to 300 kΩ, so all due care must be taken in

timing design.

Note: If pull-down resistance is made too small in an attempt to speed up the fall time, –IOH will

increase, limiting the output high-level voltage (VOH). Pull-down resistance must be set to

a suitable value taking into consideration both operation speed and the output high level.

63%

or VSS

disp

VCC

H8/3714 Series

microcontroller

312

HD6433713 Datasheet(PDF) 323 Page - Renesas Technology Corp