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7630 Datasheet(PDF) 121 Page - Renesas Technology Corp

Part # 7630
Description  8-BIT SINGLE-CHIP MICROCOMPUTER
PDF  238 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7630 Datasheet(HTML) 121 Page - Renesas Technology Corp

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7630 Group User’s Manual
$33/,&$7,21
2-55
2.4 Controller Area Network (CAN) module
Fig. 2.4.31 Acceptance filter logic
2.4.8 Message reception
The module is equipped with two physical receive buffers. This double buffer architecture allows simultaneous
CPU-processing of a previously received frame and reception/storage of a new frame by the module. To simplify
the software handling both buffers are memory mapped to the same address range (005016 to 005D16). The mod-
ule’s internal receive logic controls access to the buffers so that one buffer (later on called
foreground buffer) can
be read out by the CPU while the other buffer (
background buffer) can be written to by the module.
The user is able to switch back and forth between both buffers by one control bit; however the individual buffers
can not be addressed directly. This architecture allows sequential handling of the incoming frames on an one-by-
one basis.
The receive buffers support both standard and extended frame formats of data and remote type. The buffers hold
the following information on the received frame:
• Identifier (standard or extended),
• Frame type (data frame or remote frame),
• Data length (in case of a data frame), and
• Data bytes (in case of a data frame).
(1) Message storage
As explained above, the module features two receive buffers; after initialization both buffers are empty (unde-
fined). Upon successful reception of the first relevant (refer to section 2.4.7) frame the module will:
1. Store the frame in one of the buffers.
2. Switch the buffer to foreground to permit CPU access.
3. Flag the reception by special function bits and interrupt service request (details in section (2)).
The foreground buffer holding the message received is now under (exclusive) control of the CPU, while the
background buffer is still vacant.
After having processed the buffer contents, the CPU should release the buffer and thereby return buffer con-
trol to the module. Following to release, the buffer content is not available to the CPU any more and can not
be recaptured in any way.
Acceptance mask bit
N
Acceptance code bit
N
Identifier bit
N
Acceptance mask bit
28
Acceptance code bit
28
Identifier bit
28
Acceptance code bit
0
Acceptance mask bit
0
Identifier bit
0
29
Id match
N = 1 to 27



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