7630 datasheet(124/238 Pages) RENESAS

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7630 Group User’s Manual

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2.4 Controller Area Network (CAN) module

(3) Timing of receive sequence

The timing diagrams in Figure 2.4.34 shows the status of the internal special function bits and the contents of

the foreground receive buffer during receive sequence. Of course this timing diagram depends on the appli-

cation software and actual communication model (i.e., scheduling of messages on the bus); therefore the dia-

gram should be considered an example. The time between the occurrence of the receive interrupt request

and the clearing of this request bit depends on the interrupt system of the actual application. The latency of

the interrupt depends on the execution time of all interrupt service routines of the application unless interrupt

nesting is enabled.

The conditions used in the timing diagram are:

• Module in virgin condition (as after module reset)

• Acceptance filtering disabled (mask all identifier bits)

• Buffer content processing by CAN successful receive (CSR) interrupt service

• Execution time of CSR service routine shorter than the frames on the bus

• Interrupt system of the application optimised for minimum latency of interrupts

Fig. 2.4.34 Receive sequence timing

During a successful reception the module alters the special function bits CREC.1, IREQA.4 and CREC.0

according to the following sequence:

1. Set CREC.1 within the start-of-frame bit.

2. Set IREQA.4 and CREC.0 within the seventh bit-time of the end of frame field.

3. Clear CREC.1 after the second bit-time of the intermission field.

(4) Avoiding CAN overrun interrupts

The CAN overrun interrupt (COVR) is requested upon reception of a relevant frame when both receive buff-

ers are preoccupied by previously received frames because the CPU has not released a buffer yet. The

frame causing the CAN overrun interrupt can not be stored and hence is lost.

Ack

End of frame

Start of frame

tack–csr ≈ 6·tbt

tack–rbc ≈ 6·tbt

tack–rsb = 9·tbt

receive status bit

CAN successful receive

interrupt request bit IREQA.4

receive buffer control bit

CREC.0

CREC.1

P32/CRX

receive status bit

CAN successful receive

interrupt request bit IREQA.4

receive buffer control bit

CREC.0

CREC.1

P32/CRX

foreground receive buffer

contents CRB0 to CRBD

: undefined foreground receive buffer

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