7630 datasheet(128/238 Pages) RENESAS

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7630 Group User’s Manual

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2.4 Controller Area Network (CAN) module

mission process could be finished successfully, or a transmit abort is requested (see section 2.4.10); the

buffer can not be unlocked by clearing the transmit buffer control bit from CPU side.

(4) Issue transmission request

Finally, the transmission can be started by setting the transmission control bit of CTRM (Figure 2.4.3). Setting

this bit gives control of the buffer to the CAN module; the module attempts to transmit the frame defined by

the transmit buffer contents following the rules of the CAN specification.

After a successful transmission (without errors) the module will:

• Clear the transmit buffer control bit CTRM.5.

• Clear the transmit request bit CTRM.3.

• Set the CAN successful transmit (CST) interrupt request bit IREQA.3.

Note: The CAN successful receive interrupt (CSR) interrupt may also be requested unless disabled by the

auto-receive interrupt disable bit of CREC (Figure 2.4.16); refer to section 2.4.8, • too.

(5) Timing of transmit sequence

The timing diagram in Figure 2.4.37 shows the status of the internal special function bits during transmit

sequence if the module wins bus arbitration.

Fig. 2.4.37 Transmit sequence timing (arbitration win)

After a transmission has been requested by setting CTRM.3, the module attempts to start the transmission at

the next possible time (depending on the bus condition). During a successful transmission process the mod-

ule alters the special function bits as follows:

1. Set transmit status bit CTRM.7 shortly before the recessive to dominant edge of the start-of-frame field.

2. Set CAN successful transmit interrupt request bit IREQA.3 within the last bit-time of the end-of-frame field.

3. Clear transmit request bit CTRM.3 and transmit buffer control bit CTRM.5 within the first bit-time after the

end-of-frame field.

4. Clear transmit status bit CTRM.7 within the first bit-time after the intermission field.

Upon arbitration loss, the module changes to receiving state beginning with the next bit-time after the occur-

rence of arbitration loss. The transition from transmitting to receiving state is flagged by clearing of CTRM.7

and setting of CREC.1 (see Figure 2.4.26).

2.4.10 Abort transmission

A low priority frame in the transmit buffer may not gain bus access if the bus carries heavy traffic by medium priority

frames. The low priority frame blocks the transmit buffer and causes significant delay in scheduling of further even

high priority frames to be sent. This scenario is known as priority inversion.

Ack

End of frame

Intermission

tack–tsb ≈ 10·tbt

ttsb–sof = (0 ~ 1)·tbt

Start of frame

tack–trb = (7 ~ 8)·tbt

tack–tbc = (7 ~ 8)·tbt

tack–cst = (6 ~ 7)·tbt

P32/CRX

transmit status bit

CTRM.7

CAN successful transmit

interrupt request bit IREQA.3

transmit request bit

CTRM.3

transmit buffer control bit

CTRM.5

ttrb–sof,min = 30/f(XIN)

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