7630 datasheet(161/238 Pages) RENESAS

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APPLICATION

2.7 Watchdog timer

2-95

7630 Group User’s Manual

Fig. 2.7.2 Set-up procedure of watchdog timer

2.7.3 Watchdog timer procedure

Figure 2.7.2 shows the set-up procedure of watchdog timer.

RESET

Initialization

WDT [Address: 002E16]

CPUM [Address: 000016]

00000X002

X0XXXXXX2

X : These bits are not used in this application.

Please set these bits to “0” or “1” appropriately.

•

φ = f(XIN) divided by 2 (high-speed mode)

• The watchdog timer starts counting down.

Main processing

WDT [Address: 002E16]

X0XXXXXX2

Watchdog timer interrupt processing routine

Software reset

• The watchdog timer counters are set to the initial values

by this writing:

WDH is set to “7F16”.

WDL is set to “F16”.

• If a microcomputer runs away because of noise or others,

the watchdog timer is not initialized, and underflows.

Then the watchdog timer occurs, reset the software.

2.7.2 Watchdog timer cycle

The watchdog timer cycle varies depending on the internal clock

φ and the frequency division ratio of the

prescaler selected.

Table 2.7.1 shows the watchdog timer cycle.

Table 2.7.1 Watchdog timer cycle

f(XIN)

Internal clock selection bit

Upper byte count source selection bit

Period

(bit 6 of CPU mode register[address: 000016])

(bit 7 of Watchdog timer register[address: 002E16])

Approx. 104.9 ms

10 MHz

(

φ = f(XIN)/2 = 5 MHz)

Approx.

6.6 ms

Approx. 419.4 ms

(

φ = f(XIN)/8 = 1.25 MHz)

Approx.

26.2 ms

Approx. 131.1 ms

8 MHz

(

φ = f(XIN)/2 = 4 MHz)

Approx.

8.2 ms

Approx. 524.3 ms

(

φ = f(XIN)/8 = 1 MHz)

Approx.

32.8 ms

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