7630 datasheet(164/238 Pages) RENESAS

164 / 238 page

APPLICATION

2-98

2.9 Oscillation circuit

7630 Group User’s Manual

2.9.2 Related registers

Fig. 2.9.2 Structure of CPU mode register

CPU mode register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

CPU mode register (CPUM) [Address : 000016]

Processor mode bits

b1 b0

0 0 : Single chip mode

0 1 : Not available

1 0 : Not available

1 1 : Not available

Stack page selection bit

0 : In page 0

1 : In page 1

Not used (“0” when read, don't write “1”.)

Internal clock selection bit

0 : f(XIN)/2 (high-speed mode)

1 : f(XIN)/8 (middle-speed mode)

Not used (“0” when read, don't write “1”.)

Fig. 2.9.3 Structure of Watchdog timer register

Watchdog timer register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Watchdog timer register (WDT) [Address : 002E16]

Stop instruction disable bit

0 : Stop instruction enabled

1 : Stop instruction disabled

Executed two NOP instructions

instead of STP instruction (Note 2)

Not used (“1” when read.)

Upper byte count source selection

bit

0 : Underflow of the low order counter

1 :

φ divided by 256

Note 1: Writing to this register reloads the watchdog timer counters with the following initial

values irrespective of the value written. After reload, the watchdog timer counts down.

• The high-order counter WDH (7-bit counter) is set to “7F16”.

• The low-order counter WDL (4-bit counter) is set to “F16”.

The time-out period of the watchdog timer is

nV cycles of the internal system clock

φ .

V •

n = 524288 when the Upper byte count source selection bit is “0”.

•

n = 32768 when the Upper byte count source selection bit is “1”.

On a watchdog timer underflow, the watchdog timer interrupt (non-maskable) occurs.

Set the watchdog timer counters to the default values prevent from underflow by writing

to this register in main processing.

Once the watchdog timer has been started, it cannot be stopped except by reset.

Note 2: Once the Stop instruction is disabled, it cannot be enabled again except by reset.

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